CY8C3866AXI-040 Cypress Semiconductor Corp, CY8C3866AXI-040 Datasheet - Page 44

PSOC 3 TQFP

CY8C3866AXI-040

Manufacturer Part Number
CY8C3866AXI-040
Description
PSOC 3 TQFP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ 3 CY8C38xxr
Datasheet

Specifications of CY8C3866AXI-040

Package / Case
*
Voltage - Supply (vcc/vdd)
1.71 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
67MHz
Number Of I /o
62
Eeprom Size
2K x 8
Core Processor
8051
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 2x20b, D/A 4x8b
Oscillator Type
Internal
Peripherals
CapSense, DMA, LCD, POR, PWM, WDT
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, UART/USART, USB
Core Size
8-Bit
Processor Series
CY8C38
Core
8051
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART, USB
Maximum Clock Frequency
67 MHz
Number Of Programmable I/os
28 to 72
Number Of Timers
4
Operating Supply Voltage
0.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Controller Family/series
(8051) PSOC 3
No. Of I/o's
62
Eeprom Memory Size
2KB
Ram Memory Size
8KB
Cpu Speed
67MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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7.2.2 Datapath Module
The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is
optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band
generators and many others.
7.2.2.1 Working Registers
The datapath contains six primary working registers, which are
accessed by CPU firmware or DMA during normal operation.
Table 7-1. Working Datapath Registers
Document Number: 001-11729 Rev. *R
A0 and A1 Accumulators
D0 and D1 Data Registers
F0 and F1 FIFOs
Name
Programmable
Input from
Routing
(To/From Programmable Routing)
Function
Parallel Input/Output
6
Muxes
Input
These are sources and sinks for
the ALU and also sources for the
compares.
These are sources for the ALU
and sources for the compares.
These are the primary interface
to the system bus. They can be a
data source for the data registers
and accumulators or they can
capture data from the
accumulators or ALU. Each FIFO
is four bytes deep.
PI
PO
Description
Figure 7-8. Datapath Top Level
PHUB System Bus
Data Registers
Accumulators
FIFOs
Mask
ALU
Shift
F1
F0
D1
D0
A1
A0
R/W Access to All
Registers
7.2.2.2 Dynamic Datapath Configuration RAM
Dynamic configuration is the ability to change the datapath
function and internal configuration on a cycle-by-cycle basis,
under sequencer control. This is implemented using the 8-word
× 16-bit configuration RAM, which stores eight unique 16-bit
wide configurations. The address input to this RAM controls the
sequence, and can be routed from any block connected to the
UDB routing matrix, most typically PLD logic, I/O pins, or from
the outputs of this or other datapath blocks.
ALU
The ALU performs eight general purpose functions. They are:
Increment
Decrement
Add
Subtract
Logical AND
Logical OR
Logical XOR
Pass, used to pass a value through the ALU to the shift register,
mask, or another UDB register.
Datapath
Previous
To/From
PSoC
D0
D1
A0
A1
Chaining
®
3: CY8C38 Family
Output
Muxes
To/From
Next
Datapath
Data Sheet
6
Page 44 of 129
Output to
Programmable
Routing
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