CY8C3866AXI-040 Cypress Semiconductor Corp, CY8C3866AXI-040 Datasheet - Page 5

• Manufacturer Part Number: CY8C3866AXI-040
• Description: PSOC 3 TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C38xxr

Specifications of CY8C3866AXI-040

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x20b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Core Size: 8-Bit
• Processor Series: CY8C38
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

It also contains a separate, very low-power internal low-speed
oscillator (ILO) for the sleep and watchdog timers. A 32.768-kHz
external watch crystal is also supported for use in real-time
clock (RTC) applications. The clocks, together with
programmable clock dividers, provide the flexibility to integrate
most timing requirements.
The CY8C38 family supports a wide supply operating range from
1.71 V to 5.5 V. This allows operation from regulated supplies
such as 1.8 V ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%,
or directly from a wide range of battery types. In addition, it
provides an integrated high efficiency synchronous boost
converter that can power the device from supply voltages as low
as 0.5 V. This enables the device to be powered directly from a
single battery or solar cell. In addition, you can use the boost
converter to generate other voltages required by the device,
such as a 3.3-V supply for LCD glass drive. The boost’s output
is available on the Vboost pin, allowing other devices in the
application to be powered from the PSoC.
PSoC supports a wide range of low-power modes. These include
a 200-nA hibernate mode with RAM retention and a 1-µA sleep
mode with RTC. In the second mode, the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 1.2 mA when the CPU is running at
6 MHz, or 0.8 mA running at 3 MHz.
Document Number: 001-11729 Rev. *R
Note
6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
(OpAmp0-/Extref0, GPIO) P0[3]
(OpAmp2out, GPIO) P0[0]
(OpAmp0out, GPIO) P0[1]
(OpAmp0+, GPIO) P0[2]
(OpAmp2+, GPIO) P0[4]
(OpAmp2-, GPIO) P0[5]
(IDAC0, GPIO) P0[6]
(IDAC2, GPIO) P0[7]
(GPIO) P2[3]
(GPIO) P2[4]
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
(SIO) P12[2]
(SIO) P12[3]
Figure 2-1. 48-pin SSOP Part Pinout
Vddio0
Vddio2
Vboost
Vddd
Vccd
Vssd
Vssb
Vbat
Ind
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
5
8
1
2
3
4
6
7
9
Lines show
Vddio to I/O
supply
association
SSOP
The details of the PSoC power modes are covered in the
System”
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. The 1-wire SWV may also be
used for ‘printf’ style debugging. By combining SWD and SWV,
you can implement a full debugging interface with just three pins.
Using these standard interfaces you can debug or program the
PSoC with a variety of hardware solutions from Cypress or third
party vendors. PSoC supports on-chip break points and 4-KB
instruction and data race memory for debug. Details of the
programming, test, and debugging interfaces are discussed in
the
page 61 of this data sheet.
2. Pinouts
The Vddio pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in
through
support multiple interface voltage levels, eliminating the need for
off-chip level shifters. Each Vddio may sink up to 100 mA total to
its associated I/O pins and opamps. On the 68-pin and 100-pin
devices each set of Vddio associated pins may sink up to
100 mA. The 48-pin device may sink up to 100 mA total for all
Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all
Vddio1 plus Vddio3 associated I/O pins.
46
45
43
37
33
32
31
29
28
48
47
44
42
41
40
39
38
36
35
34
30
27
26
25
“Programming, Debug Interfaces, Resources”
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
Vddio3
P15[1] (GPIO, MHz XTAL: Xi)
P15[0] (GPIO, MHz XTAL: Xo)
Vccd
Vssd
Vddd
P15[7] (USBIO, D-, SWDCK)
P15[6] (USBIO, D+, SWDIO)
P1[7] (GPIO)
P1[6] (GPIO)
Vddio1
P1[5] (GPIO, nTRST)
P1[4] (GPIO, TDI)
P1[3] (GPIO, TDO, SWV)
P1[1] (GPIO, TCK, SWDCK)
P1[0] (GPIO, TMS, SWDIO)
P1[2] (GPIO, configurable XRES)
Figure
section on page 29 of this data sheet.
2-4. Using the Vddio pins, a single PSoC can
PSoC
[6]
[6]
®
3: CY8C38 Family
Data Sheet
Page 5 of 129
section on
Figure 2-1
“Power
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