CY8C3866AXI-040 Cypress Semiconductor Corp, CY8C3866AXI-040 Datasheet - Page 50

PSOC 3 TQFP

CY8C3866AXI-040

Manufacturer Part Number
CY8C3866AXI-040
Description
PSOC 3 TQFP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ 3 CY8C38xxr
Datasheet

Specifications of CY8C3866AXI-040

Package / Case
*
Voltage - Supply (vcc/vdd)
1.71 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
67MHz
Number Of I /o
62
Eeprom Size
2K x 8
Core Processor
8051
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 2x20b, D/A 4x8b
Oscillator Type
Internal
Peripherals
CapSense, DMA, LCD, POR, PWM, WDT
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, UART/USART, USB
Core Size
8-Bit
Processor Series
CY8C38
Core
8051
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART, USB
Maximum Clock Frequency
67 MHz
Number Of Programmable I/os
28 to 72
Number Of Timers
4
Operating Supply Voltage
0.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Controller Family/series
(8051) PSOC 3
No. Of I/o's
62
Eeprom Memory Size
2KB
Ram Memory Size
8KB
Cpu Speed
67MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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7.7 Timers, Counters, and PWMs
The timer/counter/PWM peripheral is a 16-bit dedicated
peripheral providing three of the most common embedded
peripheral features. As almost all embedded systems use some
combination of timers, counters, and PWMs. Four of them have
been included on this PSoC device family. Additional and more
advanced functionality timers, counters, and PWMs can also be
instantiated in UDBs as required. PSoC Creator allows you to
choose the timer, counter, and PWM features that they require.
The tool set utilizes the most optimal resources available.
The timer/counter/PWM peripheral can select from multiple clock
sources, with input and output signals connected through the
DSI routing. DSI routing allows input and output connections to
any device pin and any internal digital signal accessible through
the DSI. Each of the four instances has a compare output,
terminal count output (optional complementary compare output),
and programmable interrupt request line. The
Timer/Counter/PWMs are configurable as free running, one shot,
or Enable input controlled. The peripheral has timer reset and
capture inputs, and a kill input for control of the comparator
outputs. The peripheral supports full 16-bit capture.
Timer/Counter/PWM features include:
Figure 7-21. Timer/Counter/PWM
Document Number: 001-11729 Rev. *R
Clock
Reset
Enable
Capture
Kill
SDA
SCL
16-bit Timer/Counter/PWM (down count only)
Selectable clock source
PWM comparator (configurable for LT, LTE, EQ, GTE, GT)
Period reload on start, reset, and terminal count
Interrupt on terminal count, compare true, or capture
Dynamic counter reads
Timer capture mode
Count while enable signal is asserted mode
Free run mode
One Shot mode (stop at end of period)
Complementary PWM outputs with deadband
PWM output kill
Condition
START
Timer / Counter /
PWM 16-bit
ADDRESS
1 - 7
R/W
8
IRQ
TC / Compare!
Compare
Figure 7-22. I
ACK
9
2
1 - 7
C Complete Transfer Timing
DATA
7.8 I
The I
designed to interface the PSoC device with a two wire I
communication bus. The bus is compliant with Philips ‘The I
Specification’ version 2.1. Additional I
instantiated using Universal Digital Blocks (UDBs) in PSoC
Creator, as required.
To eliminate the need for excessive CPU intervention and
overhead, I
and generation of framing bits. I
or multimaster (Slave and Master). In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I
routing and allows direct connections to any GPIO or SIO pins.
I
CPU intervention. Additionally the device can wake from
low-power modes on a 7-bit hardware address match. If wakeup
functionality is required, I
two special sets of SIO pins.
I
Data transfers follow the format shown in
START condition (S), a slave address is sent. This address is 7
bits long followed by an eighth bit which is a data direction bit
(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'
indicates a request for data (READ). A data transfer is always
terminated by a STOP condition (P) generated by the master.
However, if a master still wishes to communicate on the bus, it
can generate a repeated START condition (Sr) and address
another slave without first generating a STOP condition. Various
combinations of read/write formats are then possible within such
a transfer.
2
2
C provides hardware address detect of a 7-bit address without
C features include:
8
Slave and master, transmitter, and receiver operation
Byte processing for low CPU overhead
Interrupt or polling CPU interface
Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)
7 or 10-bit addressing (10-bit addressing requires firmware
support)
SMBus operation (through firmware support - SMBus
supported in hardware in UDBs)
7-bit hardware address compare
Wake from low-power modes on address match
2
2
C peripheral provides a synchronous two wire interface
C
ACK
9
2
C specific support is provided for status detection
PSoC
1 - 7
2
C pin connections are limited to the
DATA
®
2
C operates as a slave, a master,
3: CY8C38 Family
8
2
2
C interfaces can be
C interfaces through DSI
Figure
ACK
Data Sheet
9
Page 50 of 129
7-22. After the
2
Condition
C serial
STOP
2
C
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