CY8C3866AXI-040 Cypress Semiconductor Corp, CY8C3866AXI-040 Datasheet - Page 51

• Manufacturer Part Number: CY8C3866AXI-040
• Description: PSOC 3 TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C38xxr

Specifications of CY8C3866AXI-040

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 2K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 2x20b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Core Size: 8-Bit
• Processor Series: CY8C38
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.9 Digital Filter Block
Some devices in the CY8C38 family of devices have a dedicated
HW accelerator block used for digital filtering. The DFB has a
dedicated multiplier and accumulator that calculates a 24-bit by
24-bit multiply accumulate in one system clock cycle. This
enables the mapping of a direct form FIR filter that approaches
a computation rate of one FIR tap for each clock cycle. The MCU
can implement any of the functions performed by this block, but
at a slower rate that consumes MCU bandwidth.
The PSoC Creator interface provides a wizard to implement FIR
and IIR digital filters with coefficients for LPF, BPF, HPF, Notch
and arbitrary shape filters. 64 pairs of data and coefficients are
stored. This enables a 64 tap FIR filter or up to 4 16 tap filters of
either FIR or IIR formulation.
Figure 7-23. DFB Application Diagram (pwr/gnd not shown)
The typical use model is for data to be supplied to the DFB over
the system bus from another on-chip system data source such
as an ADC. The data typically passes through main memory or
is directly transferred from another chip resource through DMA.
Document Number: 001-11729 Rev. *R
Routing
BUSCLK
Digital
Digital Filter
Block
read_data
write_data
Request
DMA
addr
System
CTRL
DMA
Bus
(PHUB)
Source
(PHUB)
Data
Data
Dest
The DFB processes this data and passes the result to another
on chip resource such as a DAC or main memory through DMA
on the system bus.
Data movement in or out of the DFB is typically controlled by the
system DMA controller but can be moved directly by the MCU.
8. Analog Subsystem
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
Flexible, configurable analog routing architecture provided by
analog globals, analog mux bus, and analog local buses.
High resolution delta-sigma ADC.
Up to four 8-bit DACs that provide either voltage or current
output.
Four comparators with optional connection to configurable LUT
outputs.
Up to four configurable switched capacitor/continuous time
(SC/CT) blocks for functions that include opamp, unity gain
buffer, programmable gain amplifier, transimpedance amplifier,
and mixer.
Up to four opamps for internal use and connection to GPIO that
can be used as high current output buffers.
CapSense subsystem to enable capacitive touch sensing.
Precision reference for generating an accurate analog voltage
for internal analog blocks.
PSoC
®
3: CY8C38 Family
Data Sheet
Page 51 of 129
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