STLC2411 STMicroelectronics, STLC2411 Datasheet
STLC2411
Specifications of STLC2411
Related parts for STLC2411
STLC2411 Summary of contents
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... Low level (up to HCI) stack or embedded stack with profiles – Support of UART and USB HCI transport layers Compliant to automotive specification AEC-Q100 1.1 Applications Features Typical applications in which the STLC2411 can be used are: Portable computers, PDA Modems Handheld data transfer devices ...
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... STLC2411 2 DESCRIPTION The STLC2411 offers a compact and complete solution for short-range wireless connectivity. It incorpo- rates all the lower layer functions of the Bluetooth ™ data packets of Bluetooth in addition to voice. The embedded controller can be used to run the Blue- ™ tooth protocol and application layers if required. The software is located in an external memory accessed through the external memory interface ...
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... Note the source/sink current under worst-case conditions according to the drive capability. (See table 8, pad information for value of X). 3.4 Current Consumption Table 8. Typical power consumption of the STLC2411 and External STM Flash (M28R400CB) using UART (VDD = VDD Flash = PLLVDD = 1.8V, VDDIO = 3.3V) (Indicative only) ...
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... STLC2411 4 BLOCK DIAGRAM AND ELECTRICAL SCHEMA Figure 2. Block Diagram and Electrical Schematic V DD 100nF V DDIO 100nF V DDIO 100nF 13 RADIO RF BUS I/F (*) 22pF LPOCLKP Y2 32kHz 22pF LPOCLKN VDDPLL V DD 100nF (*) If a low-power clock is available, it can be connected to the LPOCLKP pin in stead of using a crystal ...
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... Pin Description and Assignment Table 9 shows the pin list of the STLC2411. There are 107 digital functional pins and 22 supply pins. The column "PU/PD" shows the pads implementing an internal weak pull-up/down, to fix value if the pin is left open. This cannot replace an external pull-up/down. The pads are grouped according to three different power supply values, as shown in column " ...
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... STLC2411 Table 9. STLC2411 Pin List Name Pin # Interface to external memory (supports Mbyte Flash and byte access for up to1 Mbyte RAM.) int1 D2 External Interrupt used also as external wakeup int2 D1 Second external interrupt boot G14 Select external boot from EMI or internal from ROM ...
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... Table 9. STLC2411 Pin List (continued) Name Pin # data6 M12 External data bit 6 data7 M13 External data bit 7 data8 M14 External data bit 8 data9 K13 External data bit 9 data10 K14 External data bit 10 data11 J12 External data bit 11 data12 J13 External data bit 12 ...
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... STLC2411 Table 9. STLC2411 Pin List (continued) Name Pin # uart2_rxd G3 Uart2 receive data I2C interface i2c_dat C1 I2C data pin i2c_clk D3 I2C clock pin USB interface usb_dn G1 USB - pin (Needs a series resistor of 27 usb_dp G2 USB + pin (Needs a series resistor of 27 GPIO interface gpio0 ...
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... Table 9. STLC2411 Pin List (continued) Name Pin # test A2 Test mode JTAG interface ntrst A3 JTAG pin tck B3 JTAG pin tms C4 JTAG pin tdi A4 JTAG pin tdo B4 JTAG pin (should be left open) PCM interface pcm_a F2 PCM data pcm_b F1 PCM data pcm_sync E1 PCM 8kHz sync ...
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... STLC2411 Table 9. Pin List (continued) Name Pin # Power Supply vsspll D14 PLL ground vddpll C13 1.8V supply for PLL vdd B7 1.8V Digital supply vdd K2 1.8V Digital supply vdd L12 1.8V Digital supply vdd L14 1.8V Digital supply vdd M4 1.8V Digital supply ...
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... QoS Flush. See also 7.9. QoS. – Synchronization: the local and the master BT clock are available via HCI commands for synchronization of parallel applications on different slaves. – L2CAP Flow & Error control – LMP Improvements – LMP SCO handling – Parameter Ranges update STLC2411 11/25 ...
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... GENERAL SPECIFICATION 7.1 SYSTEM CLOCK The STLC2411 works with a single clock provided on the XIN pin. The value of this external clock should be any integer value from 12 … 33 MHz ±20ppm (overall). 7.1.1 SLOW CLOCK The slow clock is used by the baseband as reference clock during the low power modes. The slow clock requires an accuracy of ± ...
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... The Master and the Slaves predefined instant, switch to the new channel distribution scheme. No longer jammed channels are re-inserted into the channel distribution scheme. AFH uses the same hop frequency for transmission as for reception. SCO SCO ACL ACL STLC2411 SCO SCO t AFH(79) WLAN used frequency t AFH(19<N<79) ...
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... PARK is programmed. Once one of these two states is entered the STLC2411 goes in Sleep Mode. After that, the Host may decide to place the STLC2411 in Deep Sleep Mode by putting the UART LINK in low power mode. The Deep Sleep Mode allows smaller power consumption. When the STLC2411 needs to send or receive a packet (e ...
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... Mode outside the receiver activity. The selection between Sleep Mode and Deep Sleep Mode depend on the UART activity like in SNIFF or PARK. 7.10.3 NO CONNECTION If the Host places the UART in low power and there is no activity, then the STLC2411 can be placed in Deep Sleep Mode. 7.10.4 ACTIVE LINK When there is an active link (SCO or ACL), the STLC2411 cannot go in Deep Sleep Mode whatever the UART state is ...
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... GHz ISM bandwidth usage for both devices while preserving the quality of some critical types of link. 7.12.2 Algorithm 2: WLAN master In case the STLC2411 has to cooperate collocated scenario, with a WLAN chip not supporting a PTA based algorithm, it's possible to put in place a simpler mechanism. The interface is reduced to 1 line: ...
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... HCI UART transport layer: – all HCI commands as described in the Bluetooth – ST specific HCI command (check STLC2411 Software Interface document for more information) – RXD, TXD, CTS, RTS on permanent external pins – 128-byte FIFOs, for transmit and for receive – ...
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... Bluetooth baseband with ACL packets. The samples are decoded by the embedded ARM CPU (the samples were encoded, for compression, in SBC or MP3 format) and then sent to a stereo codec though the SPI interface. The application is described in the figure below. Figure 7. STLC2411 Bluetooth SPI slave mode 32 bits reception To support this application, the data size is 32 bits ...
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... ARM7TDMI application when connected with the standard ARM7 devel- opment tools. 8.6 RF Interface The STLC2411 radio interface is compatible to BlueRF (unidirectional RxMode2 for data and unidirection- al serial interface for control). 8.7 PCM voice interface The voice interface is a direct PCM interface to connect to a standard CODEC (e.g. STw5093 or STw5094) including internal decimator and interpolator filters. The data can be linear PCM (13-16bit), µ ...
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... STLC2411 interface is programmable to be CVSD, A-Law or µ-Law. The PCM block is able to manage the PCM bus with timeslots. PCM clock and data are in master mode available at 2 MHz or at 2.048 MHz to allow interfacing of stan- dard codecs. The four signals of the PCM interface are: – ...
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... HCI UART TRANSPORT LAYER The UART Transport Layer is specified by the Bluetooth tween a host controller (STLC2411) and a host (e.g. PC), via a serial line. The objective of this HCI UART Transport Layer is to make it possible to use the Bluetooth serial interface between two UARTs on the same PCB. The HCI UART Transport Layer assumes that the UART communication is free from line errors ...
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... HCI USB TRANSPORT LAYER The USB Transport Layer has been specified by the Bluetooth between a host controller (STLC2411) and a host (e.g. PC), via a USB interface. The USB Transport Layer is completely implemented in SW. It accepts HCI messages from the HCI Layer, prepares it for transmis- sion over a USB bus, and sends it to the USB Driver. It reassembles the HCI messages from USB data received from the USB Driver, and sends these messages to the HCI Layer. The Transport Layer does not interprete the contents (payload) of the HCI messages ...
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... MIN. TYP. MAX. 0.040 0.047 0.006 0.032 0.010 0.012 0.014 0.310 0.315 0.321 0.256 0.310 0.315 0.321 Body 1.20mm 0.256 0.018 0.020 0.022 0.024 0.029 0.035 Fine Pitch Ball Grid Array 0.003 STLC2411 OUTLINE AND MECHANICAL DATA TFBGA132 7146828 A 23/25 ...
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... STLC2411 Table 15. Revision History Date Revision June 2004 24/25 1 First Issue Description of Changes ...
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