STLC2416 STMicroelectronics, STLC2416 Datasheet
STLC2416
Specifications of STLC2416
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STLC2416 Summary of contents
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... Software support – Low level (up to HCI) stack or embedded stack with profiles – Support of UART and USB HCI transport layers. 1.1 Applications Features Typical applications in which the STLC2416 can be used are: Cable replacement Portable computers, PDA Modems Handheld data transfer devices ...
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... DESCRIPTION The STLC2416 from STMicroelectronics is a Bluetooth™ baseband controller with integrated 4 Mbit flash mem- ory. Together with a Bluetooth™ Radio this product offers a compact and complete solution for short-range wire- less connectivity. It incorporates all the lower layer functions of the Bluetooth™ protocol. ...
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... Note the source/sink current under worst-case conditions according to the drive capability. (See table 8, pad information for value of X). 3.4 Current Consumption Table 8. Typical power consumption of the STLC2416 (VDD = VDD Flash = PLLVDD = 1.8V, VDDIO = 3.3V) (Indicative only) STLC2416 State Standby (no low power mode) ...
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... STLC2416 4 Block Diagram and Electrical Schema Figure 2. Block Diagram and Electrical Schematic V DD 100nF V DDIO 100nF V DDIO 100nF 13 RADIO RF BUS I/F (*) 22pF LPOCLKP Y2 32kHz 22pF LPOCLKN VDDPLL V DD 100nF XIN (*) If a low-power clock is available, it can be connected to the LPOCLKP pin in stead of using a crystal (**) For device testing only (should not be connected in the application ...
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... Pin Description and Assignment Table 9 shows the pin list of the STLC2416. There are 91 functional pins of which 25 are used for device testing only (should not be connected in the application) and 24 supply pins. The column "PU/PD" shows the pads implementing an internal weak pull-up/down, to fix value if the pin is left open. This cannot re- place an external pull-up/down. The pads are grouped according to two different power supply values, as shown in column " ...
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... STLC2416 Table 9. STLC2416 Pin List Name Pin # Clock and test pins xin B18 System clock nreset A18 Reset nrp A17 Flash reset nwp H3 Flash Write Protect sys_clk_req C18 System clock request lpo_clk_p V9 Low power oscillator + / Slow clock input lpo_clk_n V10 Low power oscillator - ...
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... Table 9. STLC2416 Pin List (continued) Name Pin # uart2_txd A8 Uart2 transmit data uart2_rxd A9 Uart2 receive data I2C interface i2c_dat A14 I2C data pin i2c_clk A13 I2C clock pin USB interface usb_dn A10 USB - pin (Needs a series resistor of 27 usb_dp C9 USB + pin (Needs a series resistor of 27 ...
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... STLC2416 Table 9. STLC2416 Pin List (continued) Name Pin # tms E16 JTAG pin tdi F16 JTAG pin tdo E18 JTAG pin (should be left open) PCM interface pcm_a A11 PCM data pcm_b C10 PCM data pcm_sync A12 PCM 8kHz sync pcm_clk C11 PCM clock ...
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... Table 9. STLC2416 Pin List (continued) Name Pin # Power Supply vsspll T15 PLL ground vddpll V15 1.8V supply for PLL vdd A4 1.8V Digital supply vdd F1 1.8V Digital supply vdd J1 1.8V Digital supply vdd U1 1.8V Digital supply vdd T8 1.8V Digital supply vddf K3 1.8V Digital supply Flash ...
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... STLC2416 Table 9. STLC2416 Pin List (continued) Name Pin # To be connected together on the PCB ne D3 Flash chip enable csn0 E3 External chip select bank 0 Test Only (Do NOT connect) rdn/ng C3 External read csn1 D1 External chip select bank 1 csn2 E1 External chip select bank 2 addr0 F3 External address bit 0 ...
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... QoS Flush. See also 7.9. QoS. – Synchronization: the local and the master BT clock are available via HCI commands for synchronization of parallel applications on different slaves – L2CAP Flow & Error control – LMP Improvements – LMP SCO handling – Parameter Ranges update STLC2416 11/27 ...
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... STLC2416 6.2 Integrated Flash Memory – 4Mbit size – 8 parameter blocks of 4 Kword (top configuration) – 7 main blocks of 32 Kword – 120ns access time – see datasheet of standalone product M28R400CT for more detailed information. Figure 4. Block Addresses 3FFFF 3F000 38FFF 38000 ...
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... Vssf Flash Ground (vssf) Vssf is the reference for all voltage measurements. – Address Inputs (Addr(1-18)/Addr(0-19)), Data Input/Output (Data(0-15)/Data(0-15)), Chip Enable (ne/ csn(0)), Output Enable (ng/rdn), Write Enable (nw/wrn) are connected to and controlled by the Blue- tooth™ baseband controller. STLC2416 13/27 ...
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... When boot pin is set to `1` (connected to VDD), the STLC2416 boots on its flash – UART download boot from ROM. When boot pin is set to `0` (connected to GND), the STLC2416 boots on its internal ROM (needed to download the new firmware in the flash). When booting on the internal ROM, the STLC2416 will monitor the UART interface for approximately 1 ...
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... The Master and the Slaves predefined instant, switch to the new channel distribution scheme. No longer jammed channels are re-inserted into the channel distribution scheme. AFH uses the same hop frequency for transmission as for reception SCO SCO ACL ACL STLC2416 SCO SCO t AFH(79) WLAN used frequency t AFH(19<N<79) ...
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... PARK is programmed. Once one of these two states is entered the STLC2416 goes in Sleep Mode. After that, the Host may decide to place the STLC2416 in Deep Sleep Mode by putting the UART LINK in low power mode. The Deep Sleep Mode allows smaller power consumption. When the STLC2416 needs to send or receive a packet (e ...
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... Mode outside the receiver activity. The selection between Sleep Mode and Deep Sleep Mode depend on the UART activity like in SNIFF or PARK. 7.10.3 NO CONNECTION If the Host places the UART in low power and there is no activity, then the STLC2416 can be placed in Deep Sleep Mode. 7.10.4 ACTIVE LINK When there is an active link (SCO or ACL), the STLC2416 cannot go in Deep Sleep Mode whatever the UART state is ...
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... GHz ISM bandwidth usage for both devices while preserving the quality of some critical types of link. 7.12.2 Algorithm 2: WLAN master In case the STLC2416 has to cooperate collocated scenario, with a WLAN chip not supporting a PTA based algorithm, it's possible to put in place a simpler mechanism. The interface is reduced to 1 line: ...
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... HCI UART transport layer: – all HCI commands as described in the Bluetooth™ specification 1.1 – ST specific HCI command (check STLC2416 Software Interface document for more information) – RXD, TXD, CTS, RTS on permanent external pins – 128-byte FIFOs, for transmit and for receive – ...
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... Bluetooth baseband with ACL packets. The samples are decoded by the embedded ARM CPU (the samples were encoded, for compression, in SBC or MP3 format) and then sent to a stereo codec though the SPI interface. The application is described in the figure below. Figure 8. STLC2416 Bluetooth SPI slave mode 32 bits reception To support this application, the data size is 32 bits ...
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... ARM7TDMI application when connected with the standard ARM7 devel- opment tools. 8.6 RF Interface The STLC2416 radio interface is compatible to BlueRF (unidirectional RxMode2 for data and unidirection- al serial interface for control). 8.7 PCM voice interface The voice interface is a direct PCM interface to connect to a standard CODEC (e.g. STw5093 or STw5094) including internal decimator and interpolator filters. The data can be linear PCM (13-16bit), µ ...
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... STLC2416 The PCM block is able to manage the PCM bus with timeslots. In master mode, PCM clock and data can operate at 2 MHz or at 2.048 MHz to allow interfacing of stan- dard codecs. The four signals of the PCM interface are: – PCM_CLK : PCM clock – PCM_SYNC : PCM 8kHz sync – ...
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... The UART Transport Layer has been specified by the Bluetooth™ SIG, and allows HCI level communica- tion between a host controller (STLC2416) and a host (e.g. PC), via a serial line. The objective of this HCI UART Transport Layer is to make it possible to use the Bluetooth™ HCI over a serial interface between two UARTs on the same PCB ...
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... The USB Transport Layer has been specified by the Bluetooth™ SIG, and allows HCI level communica- tion between a host controller (STLC2416) and a host (e.g. PC), via a USB interface. The USB Transport Layer is completely implemented in SW. It accepts HCI messages from the HCI Layer, prepares it for transmission over a USB bus, and sends it to the USB Driver ...
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... Body 1.4mm 0.0098 basic 0.006 0.0039 0.0031 0.006 0.002 OUTLINE AND MECHANICAL DATA LFBGA120 Low Fine Ball Grid Array 7513355 A STLC2416 25/27 ...
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... STLC2416 Table 15. Revision History Date Revision June 2004 26/27 1 First Issue Description of Changes ...
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