ISPGDX160VA-3B208 LATTICE SEMICONDUCTOR, ISPGDX160VA-3B208 Datasheet
ISPGDX160VA-3B208
Specifications of ISPGDX160VA-3B208
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ISPGDX160VA-3B208 Summary of contents
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... N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Product Status Discontinued Active / Orderable Discontinued ...
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... LEAD-FREE PACKAGE OPTIONS * “VA” Version Only Copyright © 2004 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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... The ispGDXV I/Os are designed to withstand “live inser- tion” system environments. The I/O buffers are disabled 2 CMOS technology. during power-up and power-down cycles. When design- ing for “live insertion,” absolute maximum rating conditions for the Vcc and I/O pins must still be met. ispGDXVA Device ispGDX80VA ispGDX160VA ...
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Architecture The ispGDXV/VA architecture is different from traditional PLD architectures, in keeping with its unique application focus. The block diagram is shown below. The program- mable interconnect consists of a single Global Routing ® Pool (GRP). Unlike ispLSI devices, there ...
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I/O MUX Operation MUX1 MUX0 Data Input Selected Flexible mapping of MUXsel to MUX x change the MUX select assignment after the ispGDXV/ VA device has been soldered to the board. Figure ...
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... Commercial speed grade and in -5,-7, and -9ns Industrial D17 D16 grades in all packages. D18 D17 D21 D22 The ispGDX160VA has a device ID different from the D22 D23 ispGDX160V requiring that the latest Lattice download software be used for programming and verification. Al- D23 D24 though the ispGDX160VA and ispGDX160V are ...
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Applications The ispGDXV/VA Family architecture has been devel- oped to deliver an in-system programmable signal routing solution with high speed and high flexibility. The devices are targeted for three similar but distinct classes of end- system applications: Programmable, Random Signal ...
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Applications (Continued) Figure 5. Address Demultiplex/Data Buffering XCVR I/OA I/OB OEA OEB Address Latch D Q CLK Figure 6. Data Bus Byte Swapper XCVR D0-7 I/OA I/OB OEA OEB XCVR D8-15 I/OA I/OB OEA OEB Figure 7. Four-Port Memory Interface ...
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... I/O Reference Voltage CCIO o Capacitance (T =25 C, f=1.0 MHz) A SYMBOL PARAMETER C I/O Capacitance 1 C Dedicated Clock Capacitance 2 Erase/Reprogram Specifications PARAMETER Erase/Reprogram Cycles Specifications ispGDX160VA 1 0°C to +70°C Commercial -40°C to +85°C Industrial A PACKAGE TYPE TYPICAL PQFP BGA, fpBGA PQFP BGA, fpBGA MINIMUM 10,000 8 MIN ...
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... I/O Reference Voltage CCIO V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 1. I/O voltage configuration must be set to VCC. Specifications ispGDX160VA Figure 8. Test Load GND to V CCIO(MIN) < 1.5ns 10 CCIO(MIN CCIO(MIN) See Figure 8 Device Output * C L includes Test Fixture and Probe Capacitance ...
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... An input driving four I/O cells at 40MHz results in a dynamic I 4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals. 5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin. Specifications ispGDX160VA 1 Over Recommended Operating Conditions CONDITION – ...
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... Output Skew (tgco1 Across Chip) 1. All timings measured with one output switching, fast output slew rate setting, except 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. Specifications ispGDX160VA Over Recommended Operating Conditions DESCRIPTION 1 ...
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... Output Skew (tgco1 Across Chip) 1. All timings measured with one output switching, fast output slew rate setting, except 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. Specifications ispGDX160VA Over Recommended Operating Conditions DESCRIPTION 1 ...
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... External Timing Parameters (Continued) ispGDX160VA timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the ∆ GRP Delay with increased GRP loads. These deltas ispGDX160VA Maximum Specifications ispGDX160VA apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1) ...
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... Global Reset t 65 Global Reset to I/O Register Latch gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. Specifications ispGDX160VA 1 Over Recommended Operating Conditions 1 DESCRIPTION MIN. MAX. MIN. MAX. UNITS — ...
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... Global Reset t 65 Global Reset to I/O Register Latch gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. Specifications ispGDX160VA 1 Over Recommended Operating Conditions 1 DESCRIPTION MIN. MAX. MIN. MAX. UNITS — ...
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... Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Conditions ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions TEST CONDITION A 153Ω Active High B ...
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External Timing Parameters 1 TEST # PARAMETER COND Data Prop. Delay from Any I/O pin to Any I/O pin (4:1 MUX sel A Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX) 2 ...
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External Timing Parameters (Continued) ispGDX160V timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the ∆ GRP Delay with increased GRP loads. These deltas ispGDX160V Maximum Specifications ispGDX160V apply to any signal path ...
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Internal Timing Parameters PARAMETER # Inputs t 32 Input Buffer Delay io GRP t 33 GRP Delay grp MUX t 34 I/O Cell MUX A/B/C/D Data Delay muxd t 35 I/O Cell MUX A/B/C/D Expander Delay muxexp t 36 I/O ...
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Switching Waveforms VALID INPUT MUXSEL (I/O INPUT) t sel DATA (I/O INPUT) VALID INPUT t pd COMBINATORIAL I/O OUTPUT Combinatorial Output OE (I/O INPUT) t dis COMBINATORIAL I/O OUTPUT I/O Output Enable/Disable CLK (I/O INPUT) Clock Width ...
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Development System The ispLEVER Development System supports ispGDX design using a VHDL or Verilog language syntax. From creation to in-system programming, the ispLEVER sys- tem is an easy-to-use, self-contained design tool. Features • VHDL and Verilog Synthesis Support Available ...
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... Table 4. ispGDX160V/VA Device ID Codes DEVICE 32-BIT BOUNDARY SCAN ID CODE ispGDX160V 0000, 0000, 0011, 0101, 0011, 0000, 0100, 0011 ispGDX160VA 0001, 0000, 0011, 0101, 0011, 0000, 0100, 0011 Specifications ispGDX160V/VA allows customers using boundary scan test to have full test capability with only a single BSDL file. ...
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Boundary Scan (Continued) The ispJTAG programming is accomplished by execut- ing Lattice private instructions under the Boundary Scan State Machine. Details of the programming sequence are transparent to the user and are handled by Lattice ISP Daisy Chain Figure 11. ...
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Boundary Scan (Continued) Figure 13. Boundary Scan Waveforms and Timing Specifications TMS TDI T btch TCK TDO Data to be captured Data to be driven out Symbol t TCK [BSCAN test] clock pulse width btcp t TCK [BSCAN test] pulse ...
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Signal Descriptions Signal Name I/O Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs, each may be independently latched, registered or tristated. They can also each assume one other control function (OE, CLK/CLKEN, and ...
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... VCC 1, 17, 33, 49, 65, 89, 105, 1 121, 137, 153, 156 , 170, 184, 193 VCCIO 156 1 NC 73, 74, 179 1. VCC on ispGDX160V, VCCIO on ispGDX160VA. Specifications ispGDX160V/VA 208-Ball fpBGA D9 A12 A8 D10 N8 V10 R8 Y10 B9 C11 C9 ...
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I/O Locations: ispGDX160V/VA (Ordered by I/O Signal Name and 208-Pin PQFP Location) I/O Control 208 208 272 Signal Signal PQFP fpBGA BGA VCC I/O A0 CLK/CLKEN I/O A2 MUXsel1 4 C2 I/O A3 ...
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I/O Locations: ispGDX160V/VA (Ordered by 208-Ball BGA Location) I/O Control 208 208 272 Signal Signal PQFP fpBGA BGA I/O A3 MUXsel2 5 A1 I/O D39 MUXsel2 208 A2 I/O D36 CLK/CLKEN 205 A3 I/O D33 OE 201 A4 I/O D30 ...
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I/O Locations: ispGDX160V/VA (Ordered by 272-Ball BGA Location) I/O Control 208 208 272 Signal Signal PQFP fpBGA BGA I/O D36 CLK/CLKEN 205 A3 A3 I/O D34 MUXsel1 202 B4 A4 I/O D30 MUXsel1 198 A5 A5 I/O D24 CLK/CLKEN 190 ...
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... B38 B35 B32 B28 I/O I/O I/O I B39 B33 B29 B27 NCs are not to be connected to any active signals, Vcc or GND. 2. VCCIO on ispGDX160VA. VCC on ispGDX160V. Specifications ispGDX160V/ I/O I/O I/O Y3/ 1 D16 TOE NC 1 D13 D20 D24 CLKEN3 I/O I/O I/O NC ...
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... B36 B33 B31 I/O I/O I/O I/O I/O T B38 B37 B34 B32 B29 NCs are not to be connected to any active signals, Vcc or GND. 2. VCCIO on ispGDX160VA. VCC on ispGDX160V. Specifications ispGDX160V/ I/O I/O 1 EPEN RESET NC D17 D23 D27 I/O I/O I/O I/O Y2/ ...
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... OE I MUXsel1 I MUXsel2 I — VCC 49 50 CLK/CLKEN I I MUXsel1 I Connect Pins (NC) are not to be connected to any active signal, Vcc or GND. 2. VCCIO on ispGDX160VA. VCC on ispGDX160V. Specifications ispGDX160V/VA ispGDX160V/VA Top View 33 Data Control 2 156 VCCIO/VCC — 155 I 154 I CLK/CLKEN 153 VCC — 152 ...
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... Note: The ispGDX160VA devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, e.g. ispGDX160VA-3B208-5I. Specifications ispGDX160V/ XXXXX X Grade Blank = Commercial I = Industrial Package Q208 = 208-Pin PQFP B208 = 208-Ball fpBGA BN208 = Lead-Free 208-Ball fpBGA ...
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... FAMILY tpd (ns) 5 ispGDXVA 7 9 Note: The ispGDX160VA devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, e.g. ispGDX160VA-3B208-5I. Specifications ispGDX160V/VA INDUSTRIAL ORDERING NUMBER ispGDX160VA-5Q208I ispGDX160VA-5B208I ispGDX160VA-5B272I ispGDX160VA-7Q208I ispGDX160VA-7B208I ispGDX160VA-7B272I ispGDX160VA-9Q208I ispGDX160VA-9B208I ...