MAX1473ETJ+ Maxim Integrated Products, MAX1473ETJ+ Datasheet - Page 8

• Manufacturer Part Number: MAX1473ETJ+
• Description: RF Receiver IC RCVR ASK 315MHZ/433MHZ
• Manufacturer: Maxim Integrated Products

Specifications of MAX1473ETJ+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
8
TSSOP
2, 7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
—
—
_______________________________________________________________________________________
1
3
4
5
6
8
9
PIN
TQFN
21, 25
1, 13,
4, 30
29
31
32
10
11
12
14
15
16
17
18
19
20
22
23
24
26
27
28
—
2
3
5
6
7
8
9
DATAOUT Digital Baseband Data Output
XTALSEL
LNASRC
LNAOUT
MIXOUT
AGCDIS
PWRDN
PDOUT
MIXIN1
MIXIN2
NAME
XTAL1
LNAIN
AGND
AGND
DGND
XTAL2
DVDD
AVDD
IRSEL
DFFB
IFIN1
IFIN2
V
DFO
DSN
OPP
DSP
N.C.
EP
DD5
1st Crystal Input. (See the Phase-Locked Loop section.)
Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.2V
low-dropout regulator and should be bypassed to AGND with a 0.1µF capacitor as close as
possible to the pin. Pin 7 must be externally connected to the supply from pin 2 and bypassed to
AGND with a 0.01µF capacitor as close as possible to the pin (see the Voltage Regulator section
and the Typical Application Circuit).
Low-Noise Amplifier Input. (See the Low-Noise Amplifier section.)
Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set
LNA input impedance. (See the Low-Noise Amplifier section.)
Analog Ground
Low-Noise Amplifier Output. Connect to mixer through an LC tank filter. (See the Low-Noise
Amplifier section.)
1st Differential Mixer Input. Connect through a 100pF capacitor to V
2nd Differential Mixer Input. Connect through a 100pF capacitor to LC tank filter from LNAOUT.
Analog Ground
Im ag e Rej ecti on S el ect P i n. S et V
unconnected to center i m ag e r ej ecti on at 375M H z. S et V
330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
Digital Ground
Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01µF
capacitor as close as possible to the pin (see the Typical Application Circuit).
AGC Control Pin. Pull high to disable AGC.
Crystal Divider Ratio Select Pin. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL
high to select divider ratio of 32.
1st Differential Intermediate Frequency Limiter Amplifier Input. Decouple to AGND with a 1500pF
capacitor.
2nd Differential Intermediate Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
bandpass filter.
Data Filter Output
Negative Data Slicer Input
Noninverting Op-Amp Input for the Sallen-Key Data Filter
Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
Positive Data Slicer Input
+5V Supply Voltage. Bypass to AGND with a 0.01µF capacitor as close as possible to the pin. For
+5V operation, V
pin 2 AVDD pin. (See the Voltage Regulator section and the Typical Application Circuit.)
Peak Detector Output
Power-Down Select Input. Drive this pin with a logic high to power on the IC.
2nd Crystal Input
No Connection
Exposed Pad (TQFN Only). Connect EP to GND.
DD5
is the input to an on-chip voltage regulator whose +3.2V output appears at the
I RS E L
= 0V to center i m ag e r ej ecti on at 315M H z. Leave IRS E L
FUNCTION
IRS E L
= V
D D
to center i m ag e r ej ecti on at 433M H z.
DD3
side of the LC tank.
Pin Description