MAX7033EUI+T Maxim Integrated Products, MAX7033EUI+T Datasheet - Page 9

• Manufacturer Part Number: MAX7033EUI+T
• Description: RF Receiver IC RX 315MHZ/433MHZ ASK
• Manufacturer: Maxim Integrated Products
• Type: Receiverr

Specifications of MAX7033EUI+T

• Package / Case: TSSOP-28
• Operating Frequency: 450 MHz
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX7033 CMOS superheterodyne receiver and a
few external components provide the complete receive
chain from the antenna to the digital output data.
Depending on signal power and component selection,
data rates as high as 33kbps Manchester (66kbps
NRZ) can be achieved.
The MAX7033 is designed to receive binary ASK data
modulated in the 300MHz to 450MHz frequency range.
ASK modulation uses a difference in amplitude of the
carrier to represent logic 0 and logic 1 data.
For operation with a single +3.0V to +3.6V supply voltage,
connect AVDD, DVDD, and V
TSSOP
28
—
—
LNAIN
DGND
DVDD
AGND
AVDD
AVDD
V
DD5
PIN
THIN QFN
5, 10
21, 25
1, 13,
24
14
13
7
28
3
2
—
_______________________________________________________________________________________
LNASRC
LNA
DETECTOR
4
3.2V REG
XTALSEL
DIVIDE
PHASE
16
÷1
315MHz/433MHz ASK Superheterodyne
BY 64
Detailed Description
÷2
NAME
XTAL2
N.C
EP
15
AC
AUTOMATIC
CONTROL
DD5
XTAL1
1
GAIN
CRYSTAL
DRIVER
FILTER
LOOP
LNAOUT
VCO
Crystal Input 2. Can also be driven with an external reference oscillator. (See the Crystal
Oscillator section.)
No Connection
Exposed Pad (TQFN Only). Connect EP to GND.
Voltage Regulator
6
to the supply voltage.
28
XTAL2
MIXIN1 MIXIN2
8
POWER-
DOWN
27
SHDN
9
DATAOUT
25
Q
SLICER
I
DATA
Receiver with AGC Lock
REJECTION
IMAGE
IRSEL
11
90˚
20
0˚
For operation with a single +4.5V to +5.5V supply voltage,
connect V
regulator drives one of the AVDD pins to approximately
+3.2V. For proper operation, DVDD and both the AVDD
pins must be connected together. Bypass V
and the pin 7 AVDD pin to AGND with 0.01μF capacitors,
and the pin 2 AVDD pin to AGND with a 0.1μF capacitor,
all placed as close as possible to the pins.
The LNA is an nMOS cascode amplifier with off-chip
inductive degeneration, with a 3.0dB noise figure and
an IIP3 of -12dBm. The gain and noise figures are
dependent on both the antenna matching network at
the LNA input and the LC tank network between the
LNA output and the mixer inputs.
DSN
23
DSP
∑
19
DFO
FUNCTION
MIXOUT
12
DD5
Pin Description (continued)
MAX7033
to the supply voltage. An on-chip voltage
PDOUT
26
17
IFIN1
Functional Diagram
18
21
IFIN2
OPP
RSSI
Low-Noise Amplifier
100kΩ
R
DF2
IF LIMITING
FILTER
AMPS
DATA
22
DFFB
100kΩ
R
28-PIN TSSOP
DF1
PACKAGE
DD5
, DVDD,
9