PI6CV855-02LEX Pericom Semiconductor, PI6CV855-02LEX Datasheet
PI6CV855-02LEX
Specifications of PI6CV855-02LEX
Related parts for PI6CV855-02LEX
PI6CV855-02LEX Summary of contents
Page 1
... Y[0:4]) and one differential pair feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the Analog Power input (AV ). When the bypassed for test purposes. The PI6CV855-02 is able to track Spread Spectrum Clocking to reduce EMI. Pin Configuration GND ...
Page 2
... Pinout Table Function Table 08-0298 200 MHz SSTL_2 PLL Clock Driver & PI6CV855- PS8749B 11/13/08 ...
Page 3
... Application clock frequency indicates a range over which the PLL meets all of the timing parameters. 08-0298 200 MHz SSTL_2 PLL Clock Driver – – – – ± PI6CV855- μ PS8749B 11/13/08 ...
Page 4
... DC Specifications Recommended Operating Conditions Electrical Characteristics Notes: 1. Driving memory chips with 120 Ohm termination resistor for each clock output pair at 134 MHz. 08-0298 – PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver – – – – ± PS8749B ° μ 11/13/08 ...
Page 5
... The slew rate is determined from the IBIS model with test load shown in Figure 1. 3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification. 08-0298 200 MHz SSTL_2 PLL Clock Driver > 100 MHz (unless otherwise noted). CLK ± – – – – – – PI6CV855- PS8749B 11/13/08 ...
Page 6
... DDQ /2 –V DDQ /2 08-0298 =120 Figure 1. IBIS Model Output Load C=14pF –V DDQ /2 C=14pF –V DDQ /2 Figure 2. Output Load Test Circuit 6 PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver DDR SDRAM DDR SDRAM SCOPE PS8749B 11/13/08 ...
Page 7
... CLK CLK FBIN FBIN CLK CLK FBIN FBIN Yx Yx Yx, FBOUT Yx, FBOUT 08-0298 Figure 3. Cycle-to-Cycle Jitter ∑ large number of samples) Figure 4. Static Phase Offset t sk(o) Figure 5. Output Skew 7 PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver n PS8749B 11/13/08 ...
Page 8
... Outputs 08-0298 t cycle jit(per) cycle n Figure 6. Period Jitter t half period jit(hper) half period n Figure 7. Half-Period Jitter 80 sl(i), sl(o) sl(i), sl(o) Figure 8. Input and Output Slew Rates 8 PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver n+1 half period 1 2 DDQ 80% 20% 0V PS8749B 11/13/08 ...
Page 9
... N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com DESCRIPTION: 28-Pin, 173-Mil Wide, TSSOP PACKAGE CODE: L Package Code L Pb-free & Green, 28-pin 173-mil wide TSSOP 9 PI6CV855-02 200 MHz SSTL_2 PLL Clock Driver DOCUMENT CONTROL NO 1313 REVISION: D DATE: 03/09/05 0.09 .004 .008 ...