MC1496D ON Semiconductor, MC1496D Datasheet - Page 4

• Manufacturer Part Number: MC1496D
• Description: Modulator / Demodulator Balanced Mod/DeMod
• Manufacturer: ON Semiconductor

Specifications of MC1496D

• Package / Case: SOIC-14
• Maximum Operating Temperature: + 70 C
• Maximum Power Dissipation: 33 mW
• Minimum Operating Temperature: 0 C
• Modulation Type: Balanced
• Mounting Style: SMD/SMT
• Supply Current: 0.005 A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Carrier Feedthrough
carrier frequency with only the carrier applied
(signal voltage = 0).
differential amplifier by means of a bias trim potentiometer
(R1 of Figure 5).
Carrier Suppression
sideband output to carrier output for the carrier and signal
voltage levels specified.
level, as shown in Figure 22. A low value of the carrier does
not fully switch the upper switching devices, and results in
lower signal gain, hence lower carrier suppression. A higher
than optimum carrier level results in unnecessary device and
circuit carrier feedthrough, which again degenerates the
suppression figure. The MC1496 has been characterized
with a 60 mVrms sinewave carrier input signal. This level
provides optimum carrier suppression at carrier frequencies
in the vicinity of 500 kHz, and is generally recommended for
balanced modulator applications.
Thus carrier suppression can be maximized by operating
with large signal levels. However, a linear operating mode
must be maintained in the signal−input transistor pair − or
harmonics of the modulating signal will be generated and
appear in the device output as spurious sidebands of the
suppressed carrier. This requirement places an upper limit
on input−signal amplitude (see Figure 20). Note also that an
optimum carrier level is recommended in Figure 22 for good
carrier suppression and minimum spurious sideband
generation.
order to minimize carrier feedthrough. Shielding may be
necessary in order to prevent capacitive coupling between
the carrier input leads and the output leads.
Signal Gain and Maximum Input Level
as the voltage gain,
A constant dc potential is applied to the carrier input
terminals to fully switch two of the upper transistors “on”
and two transistors “off” (V
forms a cascode differential amplifier.
critical value determined by R
Carrier feedthrough is defined as the output voltage at
Carrier null is achieved by balancing the currents in the
Carrier suppression is defined as the ratio of each
Carrier suppression is very dependent on carrier input
Carrier feedthrough is independent of signal level, V
At higher frequencies circuit layout is very important in
Signal gain (single−ended) at low frequencies is defined
Linear operation requires that the signal input be below a
A
VS
+
V
V o
S
V
S
+
p I5 R
R e )2r e
R
L
E
C
(Volts peak)
E
where r e + 26 mV
= 0.5 Vdc). This in effect
and the bias current I5.
GENERAL OPERATING INFORMATION
I5(mA)
http://onsemi.com
S
.
4
Note that in the test circuit of Figure 10, V
a maximum value of 1.0 V peak.
Common Mode Swing
applied to both bases of the signal differential amplifier,
without saturating the current sources or without saturating
the differential amplifier itself by swinging it into the upper
switching devices. This swing is variable depending on the
particular circuit and biasing conditions chosen.
Power Dissipation
package should be calculated as the summation of the
voltage−current products at each port, i.e. assuming
V12 = V6, I5 = I6 = I12 and ignoring base current,
P
to pin numbers.
Design Equations
to operate the circuit with other supply voltages and input
conditions.
A. Operating Current
Assume:
then :
I
B. Common−Mode Quiescent Output Voltage
Biasing
must be set externally. Guidelines for setting up these three
levels include maintaining at least 2.0 V collector−base bias
on all transistors while not exceeding the voltages given in
the absolute maximum rating table;
The foregoing conditions are based on the following
approximations:
R5+
5
D
The common−mode swing is the voltage which may be
Power dissipation, P
The following is a partial list of design equations needed
The internal bias currents are set by the conditions at Pin 5.
The MC1496 has been characterized for the condition
The MC1496 requires three dc bias voltage levels which
= 1.0 mA and is the generally recommended value.
=
2 I5 (V6 − V14) + I5)V5 − V14 where subscripts refer
V * *f
I5
30 Vdc w [(V6, V12) − (V8, V10)] w 2 Vdc
30 Vdc w [(V8, V10) − (V1, V4)] w 2.7 Vdc
30 Vdc w [(V1, V4) − (V5)] w 2.7 Vdc
*500 W
V6 = V12, V8 = V10, V1 = V4
I5 = I6 = I12,
I
V6 = V12 = V+ − I5 R
B
tt I
where: R5 is the resistor between
where:
where:
D
, within the integrated circuit
C
for all transistors
Pin 5 and ground
f = 0.75 at T
L
S
corresponds to
A
= +25°C