S1L50992F21A200 Epson, S1L50992F21A200 Datasheet

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S1L50992F21A200

Manufacturer Part Number
S1L50992F21A200
Description
Manufacturer
Epson
Datasheet

Specifications of S1L50992F21A200

Lead Free Status / RoHS Status
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S1L50000 SERIES HIGH DENSITY GATE ARRAY
Œ
Œ
EPSON ELECTRONICS AMERICA, INC.
DESCRIPTION
EPSON Electronics America, Inc.’s S1L50000 Series is a family of ultra high-speed VLSI CMOS
gate array utilizing a 0.35 m “sea-of-gates” architecture. The S1L50000H products feature 5V
tolerant I/O buffers.
FEATURES
Ultra-high-speed, high density and low power consumption
Low voltage operation: 3.3V and 2.0V
Number of raw gates: 28,710 ~ 815,468 gates
Process
Integration
Operating Speed
I/F Levels
Input Modes
Output Modes
Output Drive
RAM
Dual Power
Operation possible at V
0.35 m 2/3/4 layer metalization CMOS process
A maximum of 815,468 gates (2 input NAND gate equivalent)
Internal gates: 140 ps (3.3V Typ), 210 ps (2.0V Typ)
Input buffer:
Output buffer: 2.12 ns (5.0V Typ) Built-in level shifter is used.
Input/Output TTL/CMOS/LVTTL compatible
TTL, CMOS, LVTTL, TTL Schmitt, CMOS Schmitt, LVTTL Schmitt, PCI
Built-in pull-up and pull-down resistors can be usable.
(2 types for each resistor value)
Normal, 3-state, bi-directional, PCI
I
(Built-in level shifter is used at 5.0V)
I
I
Asynchronous 1-port, asynchronous 2-port
Operation supported by using level-shifter circuit
Internal logic: Operation supported by low voltage
I/O Buffer:
OL
OL
OL
i
DD
150 River Oaks Pkwy
= 0.1, 1, 3, 8, 12, 24 mA selectable
= 0.1, 1, 2, 6, 12 mA selectable (at 3.3V)
= 0.05, 0.3, 0.6, 2, 4 mA selectable (at 2.0V)
= 2.0
0.2V
DATA SHEET
380 ps (5.0V Typ) Built-in level shifter is used.
400 ps (3.3V Typ), 1.30 ns (2.0V Typ)
(F/O = 2, Typical wire load)
2.02 ns (3.3 V Typ), 3.90 ns (2.0V Typ)
(C
Built-in interfaces of both high and low voltages possible
(2-input pair NAND, F/O = 2, Typical wire load)
L
= 15 pF)
i
San Jose, CA 95134
i
Tel: (408) 922-0200
i
S1L50000
Fax: (408) 922-0238
ASIC
1

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S1L50992F21A200 Summary of contents

Page 1

... S1L50000 SERIES HIGH DENSITY GATE ARRAY Œ DESCRIPTION EPSON Electronics America, Inc.’s S1L50000 Series is a family of ultra high-speed VLSI CMOS gate array utilizing a 0.35 m “sea-of-gates” architecture. The S1L50000H products feature 5V tolerant I/O buffers. Ultra-high-speed, high density and low power consumption Low voltage operation: 3 ...

Page 2

... This is the value when there are no cells, such as RAM cells. The cell use efficiency is dependent not only on the scope of the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only as an estimate 2 EPSON ELECTRONICS AMERICA, INC. DATA SHEET Number Number ...

Page 3

... Input Voltage Output Voltage Output Current/Pin Storage Temperature ** 1: Possible to use from -0.3V to 7.5V of I/O buffer voltage in the open-drain systems and input buffer in the IDC and IDH systems. *2: Possible to use for 24mA of output buffer. EPSON ELECTRONICS AMERICA, INC. DATA SHEET Symbol V -0 ...

Page 4

... Schmitt Input for Falling Edge Input *1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the IDC and IDH systems. *2: The ambient temperature range is recommended for T *3: The ambient temperature range is recommended for T 4 EPSON ELECTRONICS AMERICA, INC. DATA SHEET Symbol Min V 3 ...

Page 5

... Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the LIDC and LIDH systems or HIDC and HIDH systems. *2: The ambient temperature range is recommended for T *3: The ambient temperature range is recommended for T EPSON ELECTRONICS AMERICA, INC. DATA SHEET Symbol Min HV 4 ...

Page 6

... Pull-down Resistance* High Level Maintenance Current Low Level Maintenance Current High Level Reversal Current Low Level Reversal Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance * The values in parentheses are for the case EPSON ELECTRONICS AMERICA, INC. DATA SHEET = - Symbol Conditions ...

Page 7

... High Level Reversal Current Low Level Reversal Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance * The quiescent current is a typical value (T ** The values in parentheses are for the case of T EPSON ELECTRONICS AMERICA, INC. DATA SHEET = 0V - Symbol Conditions I Quiescent Conditions ...

Page 8

... Current Low Level Maintenance Current High Level Reversal Current Low Level Reversal Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance * The quiescent current is a typical value (T 8 EPSON ELECTRONICS AMERICA, INC. DATA SHEET = 0V - Symbol Conditions I Quiescent Conditions DDS I -- ...

Page 9

... When the customer performs all tasks to the point of logical simulations and delay simulations on engineering workstations, etc., the route taken is (2, Joint Design). When EEA performs the logical simulations, the route taken is (1, Turnkey Design). EPSON ELECTRONICS AMERICA, INC. DATA SHEET G/A Development ...

Page 10

... Viewlogic (Synopsys): TestGen (Sunrise) Place & Route ΠCadence: GateEnsemble ΠAvant!: Aquarius-GA (Apollo) Delay Calculation (Post-Route) ΠEEA: Peacock (EXDT) 10 EPSON ELECTRONICS AMERICA, INC. DATA SHEET Software Documentation Simulation Support Turnkey Design Design Verification Static Timing Analysis JTAG Insertion Test Vector Conversion i ...

Page 11

... EDA/CAE SUPPORT (continued) Static Timing ΠSynopsys: PrimeTime (DesignTime) ΠViewlogic (Synopsys): Motive Layout Verification ΠCadence: Dracula/LVS EPSON ELECTRONICS AMERICA, INC. DATA SHEET i i 150 River Oaks Pkwy San Jose, CA 95134 ASIC S1L50000 i i Tel: (408) 922-0200 Fax: (408) 922-0238 ...

Page 12

... NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of EPSON ELECTRONICS AMERICA, INC.. EEA reserves the right to make changes to this material without notice. EEA does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products ...

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