LFE2M20E-6FN484C LATTICE SEMICONDUCTOR, LFE2M20E-6FN484C Datasheet - Page 128

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LFE2M20E-6FN484C

Manufacturer Part Number
LFE2M20E-6FN484C
Description
FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet

Specifications of LFE2M20E-6FN484C

Package
484FBGA
Family Name
LatticeECP2M
Device Logic Units
19000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
304
Ram Bits
1246208

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Lattice Semiconductor
LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 144 TQFP (Cont.)
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one-to-one
connection with a package ball or pin.
Number
Pin
136
137
138
139
140
141
142
143
144
Function
Pin/Pad
VCCAUX
VCCIO0
PT6B
PT6A
PT4B
PT4A
PT2B
PT2A
GND
Bank
LFE2-6E/SE
0
0
0
0
0
0
0
-
-
Dual Function
VREF2_0
VREF1_0
Differential
4-25
C
C
C
T
T
T
Function
Pin/Pad
VCCAUX
VCCIO0
PT16B
PT16A
PT6B
PT6A
PT2B
PT2A
GND
LatticeECP2/M Family Data Sheet
Bank
0
0
0
0
0
0
0
-
-
LFE2-12E/12SE
Function
VREF2_0
VREF1_0
Dual
Pinout Information
Differential
C
C
C
T
T
T

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