LFE2M20E-6FN484C LATTICE SEMICONDUCTOR, LFE2M20E-6FN484C Datasheet - Page 30

• Manufacturer Part Number: LFE2M20E-6FN484C
• Description: FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFE2M20E-6FN484C

• Package: 484FBGA
• Family Name: LatticeECP2M
• Device Logic Units: 19000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 304
• Ram Bits: 1246208

Lattice Semiconductor
one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and
Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3)
at each input register, pipeline register and output register.
Signed and Unsigned with Different Widths
The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For
unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed
two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36
width is reached. Table 2-8 provides an example of this.
Table 2-8. Sign Extension Example
OVERFLOW Flag from MAC
The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. When two
unsigned numbers are added and the result is a smaller number than the accumulator, “roll-over” is said to have
occurred and an overflow signal is indicated. When two positive numbers are added with a negative sum and when
two negative numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and
an overflow signal is indicated. Note that when overflow occurs the overflow flag is present for only one cycle. By
counting these overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions overflow
signals for signed and unsigned operands are listed in Figure 2-27.
Figure 2-27. Accumulator Overflow/Underflow
Number
+5
-6
Unsigned
Overflow signal is generated
0101
N/A
for one cycle when this
boundary is crossed
000000101
Unsigned
9-bit
N/A
0101111100
0101111101
0101111110
0101111111
1010000001
1010000010
0101111100
0101111101
0101111110
0101111111
1010000000
1010000001
1010000010
1010000000
000000000000000101
Unsigned
Unsigned Operation
18-bit
Signed Operation
N/A
256
257
258
255
-256
-255
-254
254
255
252
253
254
252
253
2-27
000000001
111111111
111111110
111111101
000000001
111111111
111111110
111111101
000000011
000000010
000000000
000000011
000000010
000000000
Signed
1010
0101
LatticeECP2/M Family Data Sheet
Two’s Complement
+3
+2
+1
-1
-2
-3
511
510
509
0
3
2
1
0
Signed 9 Bits
000000101
111111010
Carry signal is generated for
boundary is crossed
one cycle when this
111111111111111010
000000000000000101
Two’s Complement
Signed 18 Bits
Architecture