LFE2M20E-6FN484C LATTICE SEMICONDUCTOR, LFE2M20E-6FN484C Datasheet - Page 93

• Manufacturer Part Number: LFE2M20E-6FN484C
• Description: FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFE2M20E-6FN484C

• Package: 484FBGA
• Family Name: LatticeECP2M
• Device Logic Units: 19000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 304
• Ram Bits: 1246208

Lattice Semiconductor
SERDES High Speed Data Receiver (LatticeECP2M Family Only)
Table 3-11. Serial Input Data Specifications
Input Data Jitter Tolerance
A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface stan-
dards have recognized the dependency on jitter type and have recently modified specifications to indicate toler-
ance levels for different jitter types as they relate to specific protocols (e.g. FC, etc.). Sinusoidal jitter is considered
to be a worst case jitter type.
Table 3-12. Receiver Total Jitter Tolerance Specification
RX-CID
V
V
V
V
T
Z
RL
1. This is the number of bits allowed without a transition on the incoming data stream when using DC coupling.
2. This is the typical number of bit times to re-lock to a new phase of frequency within +/- 300 ppm, assuming 8b10b encoded data and the
3. AC coupling is used to interface to LVPECL and LVDS.
Deterministic
Random
Total
Deterministic
Random
Total
Deterministic
Random
Total
Deterministic
Random
Total
1. Values are measured with PRBS 2
2. Jitter specification is limited by measurement equipment capability.
RX-RELOCK
RX-TERM
RX-DIFF-S
RX-IN
RX-CM-DC
RX-CM-AC
Symbol
Description
CDR is in lock state. When CDR is in un-lock state, or reset is applied, the total re-lock settling time will be approximately 4ms including ana-
log settle time, calibration time, and acquisition time.
RX-RL
room temperature.
S
Stream of nontransitions
(CID = Consecutive Identical Digits) @ 10
Differential input sensitivity
Input levels
Input common mode range (DC coupled)
Input common mode range (AC coupled)
CDR re-lock time
Input termination 50/75 Ohm/High Z
Return loss (without package)
3.125 Gbps
2.5 Gbps
1.25 Gbps
250 Mbps
Frequency
2
2
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
600 mV differential eye
Description
7
-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, voltages are nominal,
1

Condition
3
-12
BER
3-41
Min.
1
—
—
—
—
—
—
—
—
—
—
—
—
Min.
100
0.5
—
—
—
0
0
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Typ.
7 @ 3.125 Gbps
20 @ 1.25 Gbps
—
—
—
—
—
—
—
—
—
—
—
—
Typ.
—
—
—
50
—
—
9
Max.
0.54
0.26
0.60
0.80
0.61
0.81
0.53
0.80
0.42
0.22
0.22
0.10
V
CCRX
Max.
3000
1.2
1.5
—
—
+ 0.8
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
Units
mV, p-p
Ohms
Units
Bits
Bits
dB
V
V
V