LFE2M20E-6FN484C LATTICE SEMICONDUCTOR, LFE2M20E-6FN484C Datasheet - Page 99

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LFE2M20E-6FN484C

Manufacturer Part Number
LFE2M20E-6FN484C
Description
FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet

Specifications of LFE2M20E-6FN484C

Package
484FBGA
Family Name
LatticeECP2M
Device Logic Units
19000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
304
Ram Bits
1246208

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LatticeECP2/M sysCONFIG Port Timing Specifications (Continued)
Lattice Semiconductor
Figure 3-14. sysCONFIG Parallel Port Read Cycle
t
t
1. Re-toggling the PROGRAMN pin is not permitted until the INITN pin is high. Avoid consecutive toggling of the PROGRAMN.
2. For SED (Soft Error Detect), the SEDCLKIN operating frequency must be at least 20MHz. SEDCLKIN is derived from Master Clock Fre-
Master Clock Frequency
Duty Cycle
SUSPI
HSPI
quency that has a +/-30% variation..
Parameter
Parameter
WRITEN
SOSPI Data Setup Time Before CCLK
SOSPI Data Hold Time After CCLK
CCLK
CS1N
BUSY
D[0:7]
*n = last byte of read cycle.
CSN
Selected value - 30%
Over Recommended Operating Conditions
Min.
40
t
t
Description
SUCS
SUWD
Byte 0
t
BSCL
3-47
Byte 1
t
CORD
Selected value + 30%
Max.
t
60
DCB
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
t
Byte 2
BSCYC
t
BSCH
Byte n*
Min.
t
t
7
2
HCS
HWD
Units
MHz
Max.
%
Units
ns
ns

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