IDT77V1253L25PGI IDT, Integrated Device Technology Inc, IDT77V1253L25PGI Datasheet - Page 16

• Manufacturer Part Number: IDT77V1253L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1253L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 3
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
PHY-ATM Interface
such as segmentation and reassembly (SAR) and switching chips. MODE[1:0]
are used to select the configuration of this interface, as shown in the table below.
ATM Forum. It has separate transmit and receive channels and specific
handshaking protocols. UTOPIA Level 2 has dedicated address signals for
both the transmit and receive directions that allow the ATM layer device to specify
with which of the four PHY channels it is communicating. UTOPIA Level 1 does
not have address signals. Instead, key handshaking signals are duplicated so
that each channel has its own signals. In both versions of UTOPIA, all channels
share a single transmit data bus and a single receive data bus for data transfer.
pin count characteristic allows the 77V1253 to incorporate three separate DPI
4-bit ports, one for each of the three serial ports. As with the UTOPIA interfaces,
the transmit and receive directions have their own data paths and handshaking.
UTOPIA LEVEL 2 INTERFACE OPTION
document af-phy-0039. This PHY-ATM interface is selected by setting the
MODE[1:0] pins both low.
to-PHY) direction, and a single 16-bit data bus in the receive (PHY-to-ATM)
direction. In addition to the data bus, each direction also includes a single optional
parity bit, an address bus, and several handshaking signals. The UTOPIA
address of each channel is determined by bits 4 to 0 in the Enhanced Control
Registers. Please note that the transmit bus and the receive bus operate
completely independently. The Utopia 2 signals are summarized below:
The 77V1253 PHY offers three choices in interfacing to ATM layer devices
UTOPIA is a Physical Layer to ATM Layer interface standardized by the
DPI is a low-pin count Physical Layer to ATM Layer interface. The low-
The 16-bit Utopia Level 2 interface operates as defined in ATM Forum
This mode is configured as a single 16-bit data bus in the transmit (ATM-
TXDATA[15:0]
TXPARITY
TXSOC
TXADDR[4:0]
TXEN
TXCLAV
TXCLK
RXDATA[15:0]
RXPARITY
RXSOC
RXADDR[4:0]
RXEN
RXCLAV
RXCLK
MODE[1:0]
00
01
10
PHY-ATM Interface Configuration
one 16-bit UTOPIA Level 2 port
one 8-bit UTOPIA Level 1 (Multi-PHY) port
three 4-bit Data Path Interface (DPI) ports
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
PHY to ATM
ATM to PHY
ATM to PHY
ATM to PHY
ATM to PHY
PHY to ATM
ATM to PHY
PHY to ATM
PHY to ATM
ATM to PHY
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16
determine if any of them has room to accept a cell for transmission (TXCLAV),
or has a receive cell available to pass on to the ATM device (RXCLAV). To
poll, the ATM device drives an address (TXADDR or RXADDR) then observes
TXCLAV or RXCLAV on the next cycle of TXCLK or RXCLK. A port must tri-
state TXCLAV and RXCLAV except when it is addressed.
then transfer a cell to or from it. Selection of a port is performed by driving the
address of the desired port while TXEN or RXEN is high, then driving TXEN
or RXEN low. When TXEN is driven low, TXSOC (start of cell) is driven high
to indicate that the first 16 bits of the cell are being driven on TXDATA. The ATM
device may chose to temporarily suspend transfer of the cell by deasserting
TXEN. Otherwise, TXEN remains asserted as the next 16 bits are driven onto
TXDATA with each cycle of TXCLK.
the cell that the port is holding. It does this by asserting RXEN. The PHY then
transfers the data 16 bits each clock cycle, as determined by RXEN. As in the
transmit direction, the ATM device may suspend transfer by deasserting RXEN
at any time. Note that the PHY asserts RXSOC coincident with the first 16 bits
of each cell.
fields. Odd parity is used.
ATM standard of 53 bytes, a filler byte is inserted between the 5-byte header
and the 48-byte payload. This is shown in Figure 7.
The ATM device starts by polling the PHY ports on the Utopia 2 bus to
If TXCLAV or RXCLAV is asserted, the ATM device may select that port,
In the receive direction, the ATM device selects a port if it wished to receive
TXPARITY and RXPARITY are parity bits for the corresponding 16-bit data
Figures 8 through 13 may be referenced for Utopia 2 bus examples.
Because this interface transfers an even number of bytes, rather than the
First
Last
Figure 7. Utopia Level 2 Data Format and Sequence
Bit 15
Payload byte 45
Payload byte 47
Payload byte 1
Payload byte 3
Header byte 1
Header byte 3
Header byte 5
Payload byte 5
Payload byte 46
Payload byte 48
Header byte 2
Header byte 4
Payload byte 2
Payload byte 4
Payload byte 6
stuff byte
Bit 0
IDT77V1253
4781 drw 08