IDT77V1253L25PGI IDT, Integrated Device Technology Inc, IDT77V1253L25PGI Datasheet - Page 27

• Manufacturer Part Number: IDT77V1253L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1253L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 3
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

CONTROL AND STATUS INTERFACE
UTILITY BUS
within the IDT77V1253. These registers are used to select desired operating
characteristics and functions, and to communicate status to external systems.
(AD[7:0]) where the register address is latched via the Address Latch Enable
(ALE) signal.
The Utility Bus interface is comprised of the following pins:
Read Operation
is performed as follows:
Write Operation
INTERRUPT OPERATIONS
conditions which are useful both during ‘normal’ operation, and as diagnostic
aids. Refer to the Status and Control Register List section.
When this bit is cleared (set to 0), interrupt signalling is prevented on the
respective port. The Interrupt Mask Registers allow individual masking of
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
complete register write cycle.
1. Initial condition:
2. Set up register address:
3. Read register data:
1. Initial condition:
2. Set up register address:
3. Write data:
fications)
(according to timing specification); reset WR
The Utility Bus is a byte-wide interface that provides access to the registers
The Utility Bus is implemented using a multiplexed address and data bus
Refer to the Utility Bus timing waveforms in Figures 42 - 43. A register read
A register write is performed as described below:
The IDT77V1253 provides a variety of selectable interrupt and signalling
Overall interrupt control is provided via bit 0 of the Master Control Registers.
- RD, WR, CS not asserted (logic 1)
- ALE not asserted (logic 0)
- place desired register address on AD[7:0]
- set ALE to logic 1;
- latch this address by setting ALE to logic 0.
- Remove register address data from AD[7:0]
- assert CS by setting to logic 0;
- assert RD by setting to logic 0
- wait minimum pulse width time (see AC speci-
- RD, WR, CS not asserted (logic 1)
- ALE not asserted (logic 0)
- place desired register address on AD[7:0]
- set ALE to logic 1;
- latch this address by setting ALE to logic 0.
- place data on AD[7:0]
- assert CS by setting to logic 0;
- assert WR (logic 0) for minimum time
AD[7:0], ALE, CS, RD, WR
to logic 1 to
27
different interrupt sources. Additional interrupt signal control is provided by bit
5 of the Master Control Registers. When this bit is set (=1), receive cell errors
will be flagged via interrupt signalling and all other interrupt conditions are
masked. These errors include:
5 in the Master Control Registers. INT (pin 85) will go to a low state when an
interrupt condition is detected. The external system should then interrogate the
77V1253 to determine which one (or more) conditions caused this flag, and reset
the interrupt for further occurrences. This is accomplished by reading the
Interrupt Status Registers. Decoding the bits in these bytes will tell which error
condition caused the interrupt. Reading these registers also:
LED CONTROL AND SIGNALLING
example, the RxLED outputs are described in the truth table:
to provide for a two-LED condition indicator. These could also be different colors
to provide simple status indication at a glance. (The minimum value for R should
be 330Ω, but a value closer to 1 kΩ is recommended).
TxLED Truth Table
- Bad receive HEC
- Short (fewer than 53 bytes) cells
- Received cell symbol error
- clears the (sticky) interrupt status bits in the registers that are read
- resets INT
Normal interrupt operations are performed by setting bit 0 and clearing bit
This leaves the interrupt system ready to signal an alarm for further problems.
The LED outputs provide bi-directional LED drive capability of 8 mA. As an
As illustrated in the following drawing (Figure 31), this could be connected
Cells not being transmitted
Cells being transmitted
Cells not being received
Cells being received
RxLED(2:0)
TxLED(2:0)
STATE
STATE
Figure 31.
R
R
3.3V
not being received or
(Indicates: Cells are
(Indicates: Cells
being received
or transmitted)
transmitted)
PIN VOLTAGE
PIN VOLTAGE
4781 drw 32
High
Low
High
Low
IDT77V1253
4781 tbl 11
4781 tbl 10