IDT77V1253L25PGI IDT, Integrated Device Technology Inc, IDT77V1253L25PGI Datasheet - Page 34

• Manufacturer Part Number: IDT77V1253L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1253L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 3
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
NOTE: When set to "1", these bits mask the corresponding interrupts going to the interrupt pin (INT). When set to "0", the interrupts are unmasked. These
interrupts correspond to the interrupt status bits in the Interrupt Status Registers.
ENHANCED CONTROL REGISTERS
RXREF AND TXREF CONTROL REGISTER
INTERRUPT MASK REGISTERS
Addresses: 0x07, 0x17, 0x27
Addresses: 0x08, 0x18, 0x28
Addresses: 0x40
4-0
7,6
4-3
2-0
Bit
Bit
Bit
7
6
5
4
3
2
0
7
6
5
5
1
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
0 = interrupt enabled HEC Error Cell.
0 = interrupt enabled Short Cell Error.
0 = interrupt enabled Transmit Parity Error.
0 = interrupt enabled Receive Signal Condition Change.
0 = interrupt enabled Received Cell Symbol Error.
0 = interrupt enabled Receive FIFO Overflow.
Port 0 (Reg 0x08): 00000
Port 2 (Reg 0x28): 00010
Port 1 (Reg 0x18): 00001
00 = RxREF0 (Port 0)
0000 = not looped
Initial State
0 = not reset
0 = not reset
0 = no swap
Initial State
Initial State
0 = OSC
0
0
00
Reserved.
Reserved.
Individual Port Software Reset
1 = Reset. This bit is self clearing; It is not necessary to write "0" to exit reset.
receive clock is used as the transmit line clock.
DPI mode only. Receive direction only. See description on page 29.
Utopia 2 Port Address
bits are not affected by an Individual Port Software Reset.
RxREF Source Select
Selects which of the three ports (0 to 2) is the source of RxREF.
Master Software Reset
1 - Reset. This bit is self clearing; it is not necessary write "0" to exit reset.
Reserved.
are looped back and added to the transmit stream of that same port. See Figure 6.
Transmit Line Clock (or Loop Timing Mode)
When set to 0, the OSC input is used as the transmit line clock. When set to 1, the recovered
VPI/VCI Swap
When operating in Utopia 2 Mode, these register bits determine the Utopia 2 port address. These
RxREF to TxREF Loop Select
When set to 0, TxREF is used to generate X_8 timing marker commands.
When set to 1, TxREF input is ignored, and received X_8 timing commands
bit 2: port 2
bit 1: port 1
bit 0: port 0
34
Function
Function
Function
IDT77V1253
4781 tbl 24
4781 tbl 22
4781 tbl 23