IDT77V1253L25PGI IDT, Integrated Device Technology Inc, IDT77V1253L25PGI Datasheet - Page 5

• Manufacturer Part Number: IDT77V1253L25PGI
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1253L25PGI

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 3
• Type Of Atm Phy Interface: DPI/UTOPIA
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 144
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6
AND 51.2 MBPS ATM NETWORKS
TABLE 1 — SIGNAL DESCRIPTIONS (CONTINUED):
SIGNAL NAME
SIGNAL NAME
SIGNAL NAME
TXDATA[15:0]
RXCLAV[2:0]
RXDATA[7:0]
TXCLAV[2:0]
TXDATA[7:0]
Pn_RD[3:0]
TXPARITY
RXEN[2:0]
RXPARITY
TXEN[2:0]
TXPARITY
Pn_RCLK
RXSOC
DPICLK
TXSOC
TXSOC
TXCLK
RXCLK
TXCLK
TXEN
27, 26, 25, 24, 23, 22,
32, 31, 30, 29, 28,
21, 20, 19, 18, 17
69, 70, 71, 72,
24, 23, 22, 21,
63, 64, 65, 66,
69, 70, 71, 72,
PIN NUMBER
PIN NUMBER
73, 74, 75, 76
20, 19, 18, 17
PIN NUMBER
73, 74, 75, 76
65, 66, 54
49, 48, 47
40, 41, 42
26, 25, 34
51, 49, 48
43
34
33
35
46
58
55
43
33
35
43
8-BIT UTOPIA LEVEL 1 SIGNALS (MODE[1:0] = 01)
DPI MODE SIGNALS (MODE[1:0] = 10)
Out
Out
Out
Out
Out
Out
I/O
I/O
I/O
In
In
In
In
In
In
In
In
In
In
In
In
In
In
5
Utopia Transmit Clock. This is a free running clock input.
Utopia 2 Transmit Data. An ATM d evice transfers cells across this bus to
the 77V1253 for transmission. Also see TXPARITY.
Utopia 2 Transmit Enable. Driven by an ATM device to indicate it is
transmitting data across the TXDATA bus.
Utopia 2 Transmit Data Parity. Odd parity across TXDATA[15:0]. Parity is
checked and errors are indicated in the Interrupt Status Registers, as
enabled in the Master Control Registers. No other actio n is taken in the
event of an error. Tie high or low if unused.
Utopia 2 Transmit Start of Cell. Asserted coincident with the first word of
data for each cell on TXDATA.
Utopia 1 Receive Cell Available. Indicates the cell available status of the
respective port. It is asserted when a full cell is available for retrieval
from the receive FIFO.
Utopia 1 Receive Clock. This is a free running clock input.
Utopia 1 Receive Data. When one of the three ports is selected, the
77V1253 transfers received cells to an ATM d evice across this bus. Bit 5
in the Diagnostic Control Registers determines whether RXDATA tri-states
when RXEN[2:0] are high. Also see RXPARITY.
Utopia 1 Receive Enable. Driven by an ATM device to indicate its ability
to receive data across the RXDATA bus. One for each port.
Utopia 1 Receive Data Parity. Odd parity over RXDATA[7:0].
Utopia 1 Receive Start of Cell. Asserted coincident with the first word of
data for each cell on RXDATA. Tri-statable as determined by bit 5 in the
Diagnostic Control Registers.
Utopia 1 Transmit cell Available. Indicates the availability of room in the
transmit FIFO of the re spective p ort for a full cell.
Utopia 1 Transmit Clock. This is a free running clock input.
Utopia 1 Transmit Data. An ATM d evice transfers cells across the bus to
the 77V1253 for transmission. Also see TXPARITY.
Utopia 1 Transmit Enable. Driven by an ATM device to indicate it is
transmitting data across the TXDATA bus. One for each port.
Utopia 1 Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is
checked and errors are indicated in the Interrupt Status Registers, as
enabled in the Master Control Registers. No other actio n is taken in the
event of an error. Tie high or low if unused.
Utopia 1 Transmit Start of Cell. Asserted coincident with the first word of
data for each cell on TXDATA.
DPI Source Clock for Transmit. This is the free-running clock used as the
source to geenrate Pn_TCLK.
DPI Port 'n' Receive Clock. Pn_RCLK is cycled to indicate that the
interfacing device is ready to receive a nibb le of data on Pn_RD[3:0] of
port 'n'.
DPI Port 'n' Receive Data. Cells received on port 'n' are passed to the
interfacing device across this bus. Each port has its own dedicated bus.
SIGNAL DESCRIPTION
SIGNAL DESCRIPTION
SIGNAL DESCRIPTION
4781 tbl 03
IDT77V1253