SJA1000 NXP Semiconductors, SJA1000 Datasheet - Page 14

• Manufacturer Part Number: SJA1000
• Manufacturer: NXP Semiconductors

Specifications of SJA1000

• Data Rate: 1000Kbps
• Number Of Transceivers: 1
• Power Down Mode: Sleep
• Standard Supported: CAN 2.0B
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Package Type: PDIP
• Supply Current: 15mA
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Through Hole
• Pin Count: 28
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
Table 4 Bit interpretation of the command register (CMR); CAN address 1
Notes
1. The SJA1000 will enter sleep mode if the sleep bit is set to logic 1 (sleep); there is no bus activity and no interrupt is
2. This command bit is used to clear the data overrun condition indicated by the data overrun status bit. As long as the
3. After reading the contents of the receive buffer, the microcontroller can release this memory space of the RXFIFO
4. The abort transmission bit is used when the CPU requires the suspension of the previously requested transmission,
5. If the transmission request was set to logic 1 in a previous command, it cannot be cancelled by setting the
2000 Jan 04
CMR.7
CMR.6
CMR.5
CMR.4
CMR.3
CMR.2
CMR.1
CMR.0
Stand-alone CAN controller
pending. Setting of GTS with at least one of the previously mentioned exceptions valid will result in a wake-up
interrupt. After sleep mode is set, the CLKOUT signal continues until at least 15 bit times have passed, to allow a
host microcontroller clocked via this signal to enter its own standby mode before the CLKOUT goes LOW.
The SJA1000 will wake up when one of the three previously mentioned conditions is negated: after ‘Go To Sleep’ is
set LOW (wake-up), there is bus activity or INT is driven LOW (active). On wake-up, the oscillator is started and a
wake-up interrupt is generated. A sleeping SJA1000 which wakes up due to bus activity will not be able to receive
this message until it detects 11 consecutive recessive bits (bus-free sequence). It should be noted that setting of GTS
is not possible in reset mode. After clearing of reset request, setting of GTS is possible first, when bus-free is detected
again.
data overrun status bit is set no further data overrun interrupt is generated. It is allowed to give the clear data overrun
command at the same time as a release receive buffer command.
by setting the release receive buffer bit to logic 1. This may result in another message becoming immediately
available within the receive buffer. This event will force another receive interrupt, if enabled. If there is no other
message available no further receive interrupt is generated and the receive buffer status bit is cleared.
e.g. to transmit a more urgent message before. A transmission already in progress is not stopped. In order to see if
the original message had been either transmitted successfully or aborted, the transmission complete status bit
should be checked. This should be done after the transmit buffer status bit has been set to logic 1 (released) or a
transmit interrupt has been generated.
transmission request bit to logic 0. The requested transmission may be cancelled by setting the abort transmission
bit to logic 1.
BIT
GTS
CDO
RRB
AT
TR
SYMBOL
Go To Sleep; note 1
Clear Data Overrun;
note 2
Release Receive Buffer;
note 3
Abort Transmission;
note 4
Transmission Request;
note 5
NAME
VALUE
14
1
0
1
0
1
0
1
0
1
0
reserved
reserved
reserved
sleep; the SJA1000 enters sleep mode if no CAN
interrupt is pending and there is no bus activity
wake up; SJA1000 operates normal
clear; data overrun status bit is cleared
no action
released; the receive buffer, representing the
message memory space in the RXFIFO is
released
no action
present; if not already in progress, a pending
transmission request is cancelled
absent; no action
present; a message will be transmitted
absent; no action
FUNCTION
Product specification
SJA1000