CLC018AJVJQ National Semiconductor, CLC018AJVJQ Datasheet

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CLC018AJVJQ

Manufacturer Part Number
CLC018AJVJQ
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of CLC018AJVJQ

Number Of Arrays
1
Differential Data Transmission
Yes
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Cascading Capability
No
Line Code
NRZ
On-chip Buffers
No
On-chip Mux/demux
No
Lead Free Status / RoHS Status
Not Compliant

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© 2006 National Semiconductor Corporation
CLC018
8 x 8 Digital Crosspoint Switch, 1.485 Gbps
General Description
The CLC018 is a fully differential 8x8 digital crosspoint
switch capable of operating at data rates exceeding 1.485
Gbps per channel. Its non-blocking architecture utilizes eight
independent 8:1 multiplexers to allow each output to be
independently connected to any input and any input to be
connected to any or all outputs. Additionally, each output can
be individually disabled and set to a high-impedance state.
This TRI-STATE feature allows flexible expansion to larger
switch array sizes.
Low channel-to-channel crosstalk allows the CLC018 to pro-
vide superior all-hostile jitter of 50 ps
fidelity along with low power consumption of 850 mW make
the CLC018 ideal for digital video switching plus a variety of
data communication and telecommunication applications.
The fully differential signal path provides excellent noise
immunity, and the I/Os support ECL and PECL logic levels.
In addition, the inputs may be driven single-ended or differ-
entially and accept a wide range of common mode levels
including the positive supply. Single +5V or −5V supplies or
dual +5V supplies are supported. Dual supply mode allows
the control signals to be referenced to the positive supply
(+5V) while the high-speed I/O remains ECL compatible.
The double row latch architecture utilized in the CLC018
allows switch reprogramming to occur in the background
during operation. Activation of the new configuration occurs
with a single “configure” pulse. Data integrity and jitter per-
formance on unchanged outputs are maintained during re-
configuration. Two reset modes are provided. Broadcast
reset results in all outputs being connected to input port DI0.
TRI-STATE Reset results in all outputs being disabled.
The CLC018 is fabricated on a high-performance BiCMOS
process and is available in a 64-lead plastic quad flat pack
(PQFP).
CLC018 Block Diagram
PP
. This excellent signal
DS100088
Features
n Supports SMPTE 259M, SMPTE 344M, and SMPTE
n Fully differential signal path
n Non-Blocking
n Flexible expansion to larger array sizes with very low
n Single +5/−5V or dual
n TRI-STATE outputs
n Double row latch architecture
n 64-lead PQFP package
Applications
n Routing switchers
n Production switchers
n Master control switchers
n Telecom/datacom switchers
n Storage Area Network (SAM)
n Packet switching
n ATM SONET
Key Specifications
n High speed:
n Low jitter:
n Low power; 850 mW with all outputs active
n Fast output edge speeds: 250 ps
292M
power
<
<
50 ps
100 ps
10008802
PP
PP
for rates
>
1.485 Gbps
for rates
<
±
500 Mbps
<
5V operation
1.485 Gbps
www.national.com
August 2006
10008801

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CLC018AJVJQ Summary of contents

Page 1

... TRI-STATE Reset results in all outputs being disabled. The CLC018 is fabricated on a high-performance BiCMOS process and is available in a 64-lead plastic quad flat pack (PQFP). CLC018 Block Diagram © 2006 National Semiconductor Corporation Features n Supports SMPTE 259M, SMPTE 344M, and SMPTE 292M n Fully differential signal path ...

Page 2

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V –V CC EE) V Maximum LL V Minimum LL Storage Temperature Range Lead Temp. (Soldering 4 sec.) ESD Rating Package Thermal Resistance Electrical Characteristics ...

Page 3

Electrical Characteristics ( −5V 0V; unless otherwise specified) (Note 4 Parameter Output Voltage Swing Output Voltage Range Lower Limit Output Voltage Range Upper Limit Control Inputs: Input Voltage - HIGH V ...

Page 4

Typical Performance Characteristics www.national.com 10008803 10008805 10008807 4 10008804 10008806 10008808 ...

Page 5

... IA2, IA1 and IA0 are the three bit input selection address bus. The input port to be addressed is placed on this bus. IA2 is the Most Significant Bit (MSB). If input port Order Number CLC018AJVJQ See NS Package Number VJQ64A addressed, IA2, IA1, IA0 should have asserted on them ...

Page 6

Timing Diagrams www.national.com FIGURE 1. Timing Diagram — TRI-STATE Reset FIGURE 2. Timing Diagram — “Broadcast Reset” 6 10008810 10008811 ...

Page 7

Timing Diagrams (Continued) FIGURE 3. Timing Diagram — Switch Configuration Operation INPUT INTERFACING The inputs to the CLC018 are high impedance differential inputs (see the equivalent input circuit in Figure 4). The CLC018 can be operated with either ECL or ...

Page 8

Operation (Continued) SINGLE ENDED INPUTS Differential inputs are the preferred method of providing data to the CLC018, however, there are times when the only signal available is single ended. To use the CLC018 with a single ended input, the unused ...

Page 9

Operation (Continued) FIGURE 10. 1.485 Gbps Eye Pattern POWER SUPPLIES, GROUNDING AND BYPASSING The CLC018 uses separate power supplies for control and data circuitry. Data circuitry is supplied via V circuitry via V . Supply connection supply, ...

Page 10

Operation (Continued) TABLE 1. Interfacing of the Power Supplies and Bypass Capacitors Supply Operation I/O Data Level Control Signal Low/High Connection Key Information 1. Bypass each V with a 0.01 µF capacitor. 2. Connect V ground plane power ...

Page 11

Operation (Continued) EXPANDING THE NUMBER OF INPUT PORTS Expanding the number of inputs in a switch array is accom- plished by wire-ORing the outputs together, and TRI- STATEing the outputs of the CLC018s that do not have their inputs selected. ...

Page 12

Operation (Continued) www.national.com FIGURE 12. Expanded Input Ports 12 10008821 ...

Page 13

Operation (Continued) FIGURE 13 Output Switch Array 13 10008822 www.national.com ...

Page 14

... Interface Databook, the Fairchild F100K ECL 300 Series Databook and Design Guide and the Motorola MECL Sys- tem Design Handbook. Especially useful is the National Semiconductor Transmis- sion Line RAPIDESIGNER r Sliderule and user manual AN- 905. The RAPIDESIGNER is available by calling the Na- tional Semiconductor Customer Response Center in your area and asking for either Literature Number 633200-001 (ISO Metric units) or 633201-001 (English units) ...

Page 15

Operation (Continued) FIGURE 14. Input/Output Bussing 15 10008823 www.national.com ...

Page 16

IA2 IA1 IA0 OA2 • • • • ...

Page 17

... Deutsch Tel: +49 (0) 69 9508 6208 English www.national.com Français Tel: +33 ( 8790 64-Lead PQFP Order Number CLC018AJVJQ NS Package Number VJQ64A 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness ...

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