PEF22554HTV31XP Lantiq, PEF22554HTV31XP Datasheet

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... QuadFALC Quad E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications PEF 22554 HT/E, Version 2.1 Abstract This document is an Addendum to the PEF 22554 HT/E, QuadFALC Sheet DS1, release date 2002-09. It describes data that has to be changed or added. ...

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Logic Symbol for BGA Package Page 23, Chapter 1.2, Logic Symbol Due to the slight difference (number of power supply and ground connections) between the TQFP package and the BGA package, a separate drawing is provided for the BGA. ...

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VDDR(4:1) VSSR(4:1) Receive RL1/RDIP/ROID(4:1) Line RL2/RDIN/RCLK(4:1) Interface TDI Boundary TMS Scan TCK TRS Interface TDO VDDX(8:1) VSSX(8:1) Transmit XL1/XDOP/XIOD(4:1) Line XL2/XDON/XFM(4:1) Interface Figure 1A Logic Symbol (BGA Package) Addendum Logic Symbol for BGA Package ® QuadFALC PEF 22554 V2.1 P-BGA-160 ...

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JTAG Ball Names Page 52, Chapter 2.2, Pin Definitions and Functions The BGA ball numbers are missing for the JTAG pins. They are as shown below. Table 5 Pin Definitions - Miscellaneous Pin No. Ball No. Symbol Boundary Scan/Joint ...

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Boundary Scan 4.1 JTAG Instructions Page 63, Chapter 3.4.2, Boundary Scan Interface The TAP controller instruction codes are reserved for device tests and shall not be used. 4.2 JTAG ID Page 427, Chapter 11.4.2, JTAG Boundary Scan Interface The ...

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Bipolar Violation Detection Page 68, Chapter 4.1.6, Receive Line Coding in E1 Mode The HDB3 line code or the AMI coding is provided for the data received from the ternary or the dual rail interface. rules are detected, resulting ...

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Signaling Marker Diagrams Page 180/181, Chapter 5.5.2, Transmit System Interface The following diagrams have been modified for clarity. SYPX SCLKX T TS24 TS1 XDI XSIG A ...

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Frame 1 RDO XDI RMFB XMFB A: Channel Translation Mode 0 RDO FS XDI 1) RSIGM XSIGM B: Channel Translation Mode 1 RDO FS XDI 1) RSIGM XSIGM ...

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Clock Mode Selection Page 194/200, Chapter 6.3 and Chapter 7.3, Device Initialization E1 and T1/J1 The following text has been added: The clock mode must be programmed according to the selected MCLK frequency before any XL1/2 output is enabled ...

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Port RMFB Configuration Page 269/375, Chapter 9.2/10.2, Register Description, PC(4:1) The following text has been added: RMFB is only valid, if the receive buffer is not bypassed. 12 Port RSIG Configuration Page 270/376, Chapter 9.2/10.2, Register Description, PC(4:1) The ...

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Absolute Maximum Ratings Page 420, Chapter 11.1, Absolute Maximum Ratings The allowed voltage range has been increased. The following values and the text below the table have changed: Parameter IC supply voltage (pads, digital) IC supply voltage (core, digital) ...

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DC Characteristics Page 422/423, Chapter 11.3, DC Characteristics The transmitter output maximum leakage value and receiver maximum input voltage have been changed. Parameter Transmitter leakage current Receiver peak voltage of a mark (at RL1 or RL2) Receiver differential peak ...

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System Interface Marker Timing (Receive) Page 437, Chapter 11.4.6, AC Characteristics, System Interface The timing figure has been modified for clarity. The timing values have been corrected. positive edge timing SCLKR RDO RSIG RSIGM 1(A) DLR RFM RMFB FREEZE ...

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SYPR/SYPX Timing Page 438/439, Chapter 11.4.6, AC Characteristics, System Interface The output timing has been corrected as shown in the table below. SCLKR SCLKX SYPR SYPX XMFS Figure 100 SYPR/SYPX Marker Timing Table 80 SYPR/SYPX Timing Parameter Values No. ...

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Table 80 SYPR/SYPX Timing Parameter Values (cont’d) No. Parameter SCLKR Output Mode 3A SYPR/SYPX setup time 4A SYPR/SYPX hold time 5A XMFS inactive setup time 6A XMFS setup time 7A XMFS hold time Addendum QuadFALC SYPR/SYPX Timing Limit Values Min. ...

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Marker Output Timing Parameters Page 440, Chapter 11.4.6, AC Characteristics, System Interface The output timing has been corrected as shown in the table below. SCLKR SCLKX XMFB DLX XSIGM 1) active edge can be programmed to be positive or ...

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XDI/XSIG Timing Parameters Page 441, Chapter 11.4.6, AC Characteristics, System Interface The timing has been corrected as shown in the table below. SCLKR SCLKX XDI XSIG 1) active edge can be programmed to be positive or negative Figure 101 ...

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Table 81 XDI/XSIG Timing Parameter Values (cont’d) No. Parameter 3A XSIG setup time 4A XSIG hold time 21 SYNC Input Timing Parameters Page 446, Chapter 11.4.6, AC Characteristics, System Interface The input timing has been relaxed as shown in the ...