TFRA84J131BL-3-DB LSI, TFRA84J131BL-3-DB Datasheet
TFRA84J131BL-3-DB
Specifications of TFRA84J131BL-3-DB
Related parts for TFRA84J131BL-3-DB
TFRA84J131BL-3-DB Summary of contents
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... The Register Description and the System Design Guide. These documens are available on a password-protected web- site. The Ultraframer Product Description and the Ultraframer Hardware Design Guide (this document). These documents are available on the public website shown below (select Mappers/MUXes). If the reader displays this document using Acrobat Reader point ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Contents 1 Introduction ........................................................................................................................................................................1 2 Pin Information ...................................................................................................................................................................5 2.1 Ball Diagram ................................................................................................................................................................5 2.2 Package Pin Assignments ...........................................................................................................................................6 2.3 Pin Assignment Matrix ...............................................................................................................................................16 2.4 Pin Types ...................................................................................................................................................................19 2.5 Pin Definitions ............................................................................................................................................................20 3 Absolute Maximum Ratings .............................................................................................................................................30 3.1 Handling Precautions ................................................................................................................................................30 3.2 Thermal Parameters (Definitions and Values) ...........................................................................................................30 3.3 Reliability ...................................................................................................................................................................31 4 Electrical Characteristics .................................................................................................................................................32 4 ...
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... Table 2-10. Shared Low-Speed Line Out .............................................................................................................................23 Table 2-11. TDM Concentration Highway (CHI) In ...............................................................................................................24 Table 2-12. TDM Concentration Highway (CHI) Out ............................................................................................................24 Table 2-13. Framer (FRM) Block, CHI/Parallel System Bus (PSB) Clock and Sync ............................................................25 Table 2-14. Reference Clocks ..............................................................................................................................................25 Table 2-15. Clock Generator ................................................................................................................................................26 Table 2-16. Microprocessor Interface ...................................................................................................................................27 Table 2-17. Boundary Scan (IEEE® ...
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... Figure 5-2. NSMI Clock and Data Diagram for M13 NSMI Mode (NSMI <---> M13 <---> DS3 External I/O) .......................35 Figure 5-3. NSMI Clock and Data Diagram for E13 NSMI Mode 1 (NSMI <---> E13 <---> E3 External I/O)........................35 Figure 5-4. NSMI Clock and Data Diagram for Framer (FRM) NSMI Mode .........................................................................36 Figure 5-5. Shared Low-Speed Line Clock and Data Timing ...............................................................................................37 Figure 5-6 ...
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... Hardware Design Guide, Revision 5 July 13, 2004 2 Pin Information 2.1 Ball Diagram The TFRA84J13 Ultraframer is housed in a 909-pin plastic ball grid array. Figure 2-1 shows the ball assignment viewed from the top of the package. The pins are spaced on a 1.0 mm pitch Figure 2-1. Ultraframer Package Diagram (Top View) Agere Systems Inc ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 2.2 Package Pin Assignments Table 2-1. Package Pin Assignments Signal Name ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] ADDR[8] ADDR[9] ADDR[10] ADDR[11] ADDR[12] ADDR[13] ADDR[14] ADDR[15] ADDR[16] ADDR[17] ADDR[18] ADDR[19] ADDR[20] ADSN NC NC CG_PLLCLKOUT CLKIN_PLL CSN NC NC ...
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... LINERXCLK[69] D7 LINERXCLK[70] E8 LINERXCLK[71] F9 LINERXCLK[72] E7 LINERXCLK[73] D6 LINERXCLK[74] G8 LINERXCLK[75] B4 LINERXCLK[76] F7 LINERXCLK[77] J9 LINERXCLK[78] F4 LINERXCLK[79] C1 LINERXCLK[80] H9 LINERXCLK[81] E5 LINERXCLK[82] TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Pin F6 A10 A12 H14 D14 A16 E17 B18 D19 H20 D21 B24 F22 B28 A29 H24 A32 D29 D30 H26 E30 F29 L30 M27 ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-1. Package Pin Assignments (continued) Signal Name LINERXCLK[83] LINERXCLK[84] LINERXCLK[85] LINERXCLK[86] LINERXDATA[1] LINERXDATA[2] LINERXDATA[3] LINERXDATA[4] LINERXDATA[5] LINERXDATA[6] LINERXDATA[7] LINERXDATA[8] LINERXDATA[9] LINERXDATA[10] LINERXDATA[11] LINERXDATA[12] LINERXDATA[13] LINERXDATA[14] LINERXDATA[15] LINERXDATA[16] LINERXDATA[17] LINERXDATA[18] LINERXDATA[19] LINERXDATA[20] LINERXDATA[21] LINERXDATA[22] LINERXDATA[23] LINERXDATA[24] LINERXDATA[25] LINERXDATA[26] ...
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... AD30 LINETXDATA[3] AG32 LINETXDATA[4] AE29 LINETXDATA[5] AE27 LINETXDATA[6] AJ28 LINETXDATA[7] AK29 LINETXDATA[8] AH28 LINETXDATA[9] AH27 LINETXDATA[10] AM31 LINETXDATA[11] AL28 LINETXDATA[12] TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Pin AL26 AM27 AG22 AL30 AG20 AG24 AG25 AK19 AL19 AF17 AJ25 AH7 AN18 AJ12 AK12 AN16 AK14 ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-1. Package Pin Assignments (continued) Signal Name LINETXDATA[13] LINETXDATA[14] LINETXDATA[15] LINETXDATA[16] LINETXDATA[17] LINETXDATA[18] LINETXDATA[19] LINETXDATA[20] LINETXDATA[21] LINETXDATA[22] LINETXDATA[23] LINETXDATA[24] LINETXDATA[25] LINETXDATA[26] LINETXDATA[27] LINETXDATA[28] LINETXDATA[29] LINETXDATA[30] LINETXDATA[31] LINETXDATA[32] LINETXDATA[33] LINETXDATA[34] LINETXDATA[35] LINETXDATA[36] LINETXDATA[37] LINETXDATA[38] LINETXDATA[39] LINETXDATA[40] LINETXDATA[41] LINETXDATA[42] ...
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... AK27 AL29 AN32 AJ22 AK28 AG21 RXDATAEN[1] AM24 RXDATAEN[2] AP27 RXDATAEN[3] AN27 SCAN_EN AL22 SCANMODE AL23 AP29 AG23 AP31 AN31 AN28 THSCN TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Pin AL25 AP33 AP30 AP32 AL27 R1 U4 AJ24 AK6 AJ6 AL5 AL6 NC AN1 NC AM1 NC AM3 NC AM2 ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-1. Package Pin Assignments (continued) Signal Name NC NC THSCP TMS TRST TXDATAEN[1] TXDATAEN[2] TXDATAEN[3] V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 V DD15 12 12 Hardware Design Guide, Revision 5 Table 2-1. Package Pin Assignments (continued) ...
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... B10 B14 B15 B20 B21 B25 B26 B30 B33 B34 C2 C4 C32 C33 C34 D3 D5 D32 D33 D34 E2 E4 E33 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Pin V E34 DD33 V J2 DD33 V J11 DD33 V J12 DD33 V J15 DD33 V J16 DD33 V J19 DD33 V J20 DD33 V J23 ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-1. Package Pin Assignments (continued) Signal Name V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33 V DD33A_SFPLL Hardware Design Guide, Revision 5 Table 2-1. Package Pin Assignments (continued) Pin Signal Name ...
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... Y19 Y20 Y21 Y32 AA3 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA32 AE3 AE32 AF3 AF32 AG16 AG19 AJ7 AJ8 V SSA_SFPLL AJ9 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Pin V AJ10 SS V AJ11 SS V AK3 SS V AK7 SS V AK8 SS V AK9 SS V AK10 SS V ...
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... Hardware Design Guide, Revision 5 July 13, 2004 2.4 Pin Types Table 2-3 describes each type of input, output, and I/O pin used in the Ultraframer device. Table 2-3. Pin Types Type Label I LVCMOS Input, LVTTL Switching Thresholds LVCMOS Input, LVTTL Switching Thresholds with Internal LVCMOS Input, LVTTL Switching Thresholds with Internal 50 k Pull-Up Resistor ...
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... Framer High-Speed Clock. The clock on this pin is internally routed IN to the DS1/E1 framers and is used as an internal master clock. This input clock can be at 155 MHz or 622 MHz. Note there are no advan- tages in using a 622 MHz clock vs. a 155 MHz clock. ...
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... In E13 NSMI mode, the signal output on this pin goes low during the overhead bytes and control bits of the E3 frame. Type O NSMI Transmit Data. NSMI output data from the framer or the M13/E13 blocks. O NSMI Transmit Clock Output. Output clock at 51.84 MHz for the DS1/E1 application ...
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... LIU. In this mode, these signals will be routed via the crossconnect to the M13 multi- plexer, E13 multiplexer, or the receive line in- puts of the DS1/E1 framers. These signals may also be used as input data for DS2/E2 ap- plications (see the System Design Guide). LINERXCLK[86:1] I/O pd Line Receive Clock [86:1]. Configurable inputs to the internal multirate crossconnect ...
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... Each of these outputs comes from the internal MRXC and can be individually set to high impedance. In certain cases, these pins can be used as inputs (input DS2/E2 clocks). More information will be published in the System Design Guide . TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Name/Description 23 ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 The transmit path is toward the high-speed fiber output and the receive path is from the high-speed input. Low-speed inputs, e.g., CHIRXDATA, on the transmit path are labeled receive. Low-speed outputs, e.g., CHITXDATA, on the receive path are labeled transmit. Table 2-11. TDM Concentration Highway (CHI) In ...
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... Normally this input is not used and the transmit clock is generated by an internal phase-lock loop which uses CLKIN_PLL as a reference. Note that if this input is used all the transmit framers must run at the same rate, either 1.544 MHz or 2.048 MHz. This signal could be used for both CHI and parallel system bus. ...
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... O Framer PLL Test Mode Output. Framer PLL clock (1.544 MHz, 2.048 MHz) selected by the device register Framer PLL Input Clock Mode Select Bits. The settings of these mode select pins must correspond to the frequency of CLKIN_PLL as shown below. MODE[2:0]_PLL CLKIN_PLL 000 Reserved 001 51 ...
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... TFRA84J13 device would be connected to address bit byte-addressable system address bus. Note: The Ultraframer is little endian, i.e., the least significant byte is stored in the lowest address and the most significant byte is stored in the highest address. Care must be exercised in connection with microprocessors that use big en- dian byte ordering ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 2-17. Boundary Scan (IEEE Pin Symbol AN22 TCK AP23 TDI AN23 TMS AG26 TRST AJ21 TDO Table 2-18. General-Purpose Interface Pin Symbol AK18 RSTN AJ24 PMRST AL20 IC3STATEN AP24 SCK1 AM23 SCK2 AJ23 SCAN_EN AK20 SCANMODE AL21 IDDQ Table 2-19 ...
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... AM12, AG11, AG13, D18, A19, AL12, E19 Agere Systems Inc. TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Symbol Type Name/Description V — Common power signals for 1 DD15 V — Common power signals for 3 DD33 V — Common ground signals. SS Symbol Type Name/Description No Connect NC No Connects. These pins are not used in the Ultraframer device ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 3 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability ...
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... LFPM and 500 LFPM (linear feet per minute), which JMA is calculated using the following formula: JMA is calculated using the following formula: JB 12.8 9.5 8 2.5 7 FIT (Per Device Hours) 36 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 is calculated using JC is calculated using JT Temperature °C/Watt MTBF Activation Energy 7 2. hours 0.7eV 31 ...
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... Internal reference voltage is used if UMPR_LVDS_REF_SEL = 1, or else external voltage is used. 4.2 Recommended Powerup Sequence The Ultraframer device requires dual power supplies, a 3.3 V supply for the I/O and a 1.5 V supply for the core. During power up, RSTN should be held low (holding the device in reset) and IC3STATEN should be held low (3-stating all output buffers) ...
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... Test Conditions Input Buffer Parameters < 925 mV, dc—1 MHz I GPD dc— 450 MHz IDTH V (+V HYST IDTH R With build-in termination, center-tapped IN TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Min Typ Max — — 1.0* 2.0 — — V — 0.8 SS — — 1.5 Min Typ Max V — ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 5 Timing 5.1 DS3/E3 Timing Figure 5-1 shows a simplified representation of the DS3/E3 I/O. Q CLK DS3DATAINCLK DS3POSDATAIN DS3NEGDATAIN Figure 5-1. DS3/E3 Interface Diagram in M13/E13 Block Table 5-1. DS3/E3 Input Specifications Name Reference DS3POSDATAIN[3:1] DS3DATAINCLK DS3NEGDATAIN[3:1] Table 5-2. DS3/E3 Output Specifications ...
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... C11 = 0 FRAME, RAI, RSVD Position of this pulse is provisionable 0-256 bits before C11 1536 bits C11 = 0 FRAME, RAI, RSVD Position of this pulse is provisionable 0-256 bits before C11 TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Position of this pulse is provisionable 0-256 bits before M1 Cj3 = 0 Stuff = data ...
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... Note: The 193rd bit of a DS1 frame is not transmitted on the NSMI but is used to locate the FSYNC position consequence of this, signaling bits are not transported in Ultraframer. Figure 5-4. NSMI Clock and Data Diagram for Framer (FRM) NSMI Mode Table 5-3. NSMI Input Specifications ...
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... Edge Rising/Falling R DD33 Figure 5-6. CHI Clock Timing Min — 48.84 24.42 — — — TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Max Rise Max Fall Min Setup Time (ns) Time (ns) (ns) 10* 10* 15 Propagation Delay Min (ns) Max (ns) –10 50% Typ Max 2 7 — 73.24 — 36. 122.07 — ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 CHIRXGFS CHITXGFS CHIRXGCLK CHITXGCLK CHIRXDATA CHITXDATA Note: This figure assumes TFRA84J13 is programmed to sample the frame sync signal on rising edge of the bit clock. Table 5-8. CHI Interface Timing Specifications Parameter t Frame Sync Setup Time to Active CHI Clock Edge 5 t Frame Sync Hold Time from Active CHI Clock Edge ...
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... TSn B7 data sampled TSn B1 TSn B2 data sampled TSn B0 TSn B1 data sampled – – 13 data sampled TS0 B0 TS0 B1 TS0 B2 data sampled TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 TS0 B3 TS0 B4 TS0 B5 TS0 B3 TS0 B4 TS0 B2 TS0 B3 TS0 B4 TS255 B3 TS255 B4 TS255 B5 TS0 B4 TS0 B5 TS0 B2 TS0 B3 TS0 B4 TS0 B2 TS0 B3 ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 CHIRXGFS CHIRXGCLK w/ 0 offset TSn B6 w/ ¼ bit offset TSn B6 w/ ½ bit offset TSn B6 w/ bit offset = 1 TSn offset = – 1 bit offset = offset = 127, TSn B7 bit offset = 7¾ Note: For this timing diagram assumed that the frame sync signal has been programmed to be active-high, and to be sampled by the rising edge of the bit clock. Figure 5-11. Transmit CHI Timing (CMS Mode— ...
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... Table 5-10. PSB Output Specifications Name CHITXDATA[16:1] (PSB mode) CHITXGCLK Agere Systems Inc. Figure 5-12. PSB Clock and Data Timing Reference Edge Rising/Falling R/F CHIRXGCLK R/F CHITXGCLK R/F Reference Edge Rising (R) Falling (F) R/F TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Max Rise Max Fall Min Setup Time (ns) Time (ns) (ns ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 6 Reference Clocks Duty cycles indicated in the following tables should be interpreted as follows: 50% ±10% means 45%—55%; 50% ± 5% means 47.5%—52.5%. Table 6-1. Framer Input Clocks Specifications Clock Name Period Frequency (ns) THSCP/N 6.43 155.52 MHz THSCP/N 1.6 622.08 MHz Table 6-2. DS3/E3 Input Clocks Specifications ...
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... CHITXGCLK (PSB mode) 51.44 Table 6-9. DS3/E3 Output Clocks Specifications Clock Name Period (ns) DS3RXCLKOUT [3:1](DS3) 22.353 DS3RXCLKOUT [3:1](E3) 29.09 Table 6-10. Framer PLL Output Clocks Specifications Clock Name Period (ns) CG_PLLCLKOUT 647.66 CG_PLLCLKOUT 488.28 Table 6-11. Shared Low-Speed Receive Line Input/Output Clocks Specifications ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 6-12. Shared Low-Speed Transmit Line Input/Output Clocks Specifications Clock Name Period (ns) LINETXCLK (framer; DS1) LINETXCLK (framer; E1) LINETXCLK (M12) LINETXCLK (E12) LINETXCLK (M23) LINETXCLK (E23) LINETXCLK (DJA; DS1) LINETXCLK (DJA; E1) LINETXCLK (TPG; DS1) LINETXCLK (TPG; E1) Table 6-13. NSMI Input Clock Specifications ...
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... Microprocessor Interface Timing 7.1 Synchronous Write Mode The synchronous microprocessor interface mode is selected when MPMODE (pin D2 this mode, MPCLK used for the Ultraframer is the same as the microprocessor clock. Interface timing for the synchronous mode write cycle is given in Figure 7-1 and in Table ...
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... DTN DATA[15:0] (OUTPUT) Notes: MPCLK Input clock to Ultraframer MPU block. ADDR [20:0] The address will be available throughout the entire cycle, and must be stable before ADSN turns high. CSN (Input) Chip select is an active-low signal. ADSN (Input) Address strobe is active-low. ADSN must be one MPCLK clock period wide. ...
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... In lab measurements, it has never exceeded 1000 ns. Figure 7-3. Microprocessor Interface Asynchronous Write Cycle—MPMODE Pin = 0 Agere Systems Inc. Table 7-3, and for the read cycle in t CSFDSF t RWFDSF t DVDSF t DSFDTF TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Figure 7-4 and in Table 7-4. t AICSR t ADSRAI t DSNRAI t ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications Symbol Parameter MPCLK MPCLK 16 MHz Min—66 MHz Max Frequency t CSN Fall Setup and Hold to DSN Fall CSFDSF t CSN Rise to ADDR Invalid AICSR t ADDR Valid Setup and Hold to ADSN Fall ...
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... It should never exceed 50 MPCLK cycles. TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Delay Delay Unit (Min) (Max) — — ns — — ns — — ns — — ns — — ns — ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 8 Other Timing This interface may be used as either synchronous or asynchronous mode. Table 8-1. General-Purpose Inputs Specifications Name RSTN PMRST TDI and TMS Table 8-2. General-Purpose Output Specifications Name TDO 9 Hardware Design File References (IBIS, Spice, BSDL, etc.) Available upon request. ...
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... Hardware Design Guide, Revision 5 July 13, 2004 10 909-Pin PBGA Diagram Figure 10-1. Ultraframer 909-Pin PBGA Balls and Dimensions Agere Systems Inc. TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 51 ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 11 Ordering Information Table 11-1. Ordering Information Device TFRA84J131BL-21 TFRA84J131BL Hardware Design Guide, Revision 5 Package 909-pin PBGA 909-pin PBGA July 13, 2004 Comcode 700055303 700052826 Agere Systems Inc. ...
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... Frame check sequence FDL Facility data link FEAC Far-end alarm and control FEBE Far-end block error HDB3 High-density bipolar of order three Agere Systems Inc. TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 HDLC High-level data link control LIU Line interface unit LOC Loss of clock LOF Loss of frame ...
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... All Rights Reserved July 13, 2004 DS02-402BBAC-5 (Replaces DS02-402BBAC-4) Change Change Change page 42 page 45 page 46 in Table 13-1 will bring the reader to page 21 of this document, which is the first change. TFRA84J13 Ultraframer Hardware De- DS3/E3/DS2/E2/DS1/E1/DS0 sign Guide, Revi- Change Change Change page 47 page 48 page 49 ...