DJLXT386LE.B2 S E001 Intel, DJLXT386LE.B2 S E001 Datasheet
DJLXT386LE.B2 S E001
Specifications of DJLXT386LE.B2 S E001
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DJLXT386LE.B2 S E001 Summary of contents
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LXT386 QUAD T1/E1/J1 Transceiver The LXT386 is a quad short haul Pulse Code Modulation (PCM) transceiver for use in both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications. It incorporates four independent receivers and four independent transmitters in a single ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. ...
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... G.772 Performance Monitoring ........................................................................... 37 3.9 Hitless Protection Switching (HPS) ..................................................................... 37 3.10 Operation Mode Summary .................................................................................. 38 3.11 Interfacing with 5V logic ...................................................................................... 38 3.12 Parallel Host Interface ......................................................................................... 39 3.12.1 Motorola Interface .................................................................................. 40 3.12.2 Intel Interface..........................................................................................40 3.13 Interrupt Handling................................................................................................ 41 3.13.1 Interrupt Enable ...................................................................................... 41 3.13.2 Interrupt Clear ........................................................................................ 41 3.14 Serial Host Mode .................................................................................................42 4.0 Register Descriptions 5.0 JTAG Boundary Scan 5 ...
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... Receive Clock Timing Diagram ........................................................................... 66 20 JTAG Timing ....................................................................................................... 67 21 Non-Multiplexed Intel Mode Read Timing ........................................................... 68 22 Multiplexed Intel Read Timing ............................................................................. 69 23 Non-Multiplexed Intel Mode Write Timing ........................................................... 70 24 Multiplexed Intel Mode Write Timing ................................................................... 71 25 Non-Multiplexed Motorola Mode Read Timing .................................................... 72 26 Multiplexed Motorola Mode Read Timing............................................................ 73 27 Non-Multiplexed Motorola Mode Write Timing ...
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... Plastic Ball Grid Array (PBGA) Package Dimensions .................................... 82 37 100 Pin Low Quad Flat Packages (LQFP) Dimensions ...................................... 83 38 Sample LQFP Non-RoHS Package - Intel 39 Sample LQFP RoHS Package - Intel 40 Order Matrix ........................................................................................................86 Tables 1 Pin Assignments and Signal Descriptions ...........................................................11 2 Line Length Equalizer Inputs............................................................................... 28 3 Jitter Attenuation Specifications ...
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... Transmit Timing Characteristics.......................................................................... 65 44 Receive Timing Characteristics........................................................................... 66 45 JTAG Timing Characteristics .............................................................................. 67 46 Intel Mode Read Timing Characteristics ............................................................. 67 47 Intel Mode Write Timing Characteristics ............................................................. 69 48 Motorola Bus Read Timing Characteristics ......................................................... 71 49 Motorola Mode Write Timing Characteristics ...................................................... 73 50 Serial I/O Timing Characteristics......................................................................... 75 51 Transformer Specifications3 ...
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Features • Single rail 3.3V supply with 5V tolerant inputs • Low power consumption of 150mW per channel (typical) • Superior crystal-less jitter attenuator — Meets ETSI CTR12/13, ITU G.736, G.742, G.823 and AT&T Pub 62411 specifications — Optimized ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 2. LXT386 Detailed Block Diagram JTAG SERIAL/ PARALLEL PORT RTIP3 RRING3 TTIP3 TRING3 RTIP2/RRING2 TTIP2/TRING2 RTIP1/RRING1 TTIP1/TRING1 RTIP0 RRING0 MUX TTIP0 TRING0 HARDWARE / SOFTWARE CONTROL (JTAG INTERFACE) Transceiver 3 ...
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Pin Assignments and Signal Description Figure 3 shows the pin assignments for LQFP packages. For current package markings, see 7.1, “Top Label Markings” on page 84 Figure 3. LXT386 Low-Profile Quad Flat Package (LQFP) 100 Pin Assignments MOT 1 ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 4. LXT386 Plastic Ball Grid Array (PBGA) 160 Ball Assignments N/C N/C N/C TVCC B GND GND GND TVCC C N/C N/C N/C VCC D GND GND GND VCC ...
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Table 1. Pin Assignments and Signal Descriptions (Sheet 1 of 11) Ball # Pin # Symbol PBGA LQFP E1 78 MCLK E2 79 MODE DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Pin Assignments and Signal Descriptions (Sheet 2 of 11) Ball # Pin # Symbol PBGA LQFP DI: Digital Input; DO: ...
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Table 1. Pin Assignments and Signal Descriptions (Sheet 3 of 11) Ball # Pin # Symbol PBGA LQFP G2 90 D0/LOOP0 H3 91 D1/LOOP1 H2 92 D2/LOOP2 J4 93 D3/LOOP3 J3 94 D4/DLOOP0 J2 95 D5/DLOOP1 J1 96 D6/DLOOP2 K1 ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Pin Assignments and Signal Descriptions (Sheet 4 of 11) Ball # Pin # Symbol PBGA LQFP N1 19 TCLK0 TPOS0 TDATA0 TNEG0 UBS0 1. DI: Digital Input; DO: Digital ...
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Table 1. Pin Assignments and Signal Descriptions (Sheet 5 of 11) Ball # Pin # Symbol PBGA LQFP P1 22 RCLK0 RPOS0 RDATA0 RNEG0 BPV0 K4 25 LOS0 K2 99 MUX N4 TVCC0 1. ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Pin Assignments and Signal Descriptions (Sheet 6 of 11) Ball # Pin # Symbol PBGA LQFP N5 27 TTIP0 P5 28 TRING0 N6 TGND0 P7 30 RTIP0 N7 31 RRING0 L6, ...
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... INT goes Low to flag the host when the LXT386 changes state (see details in the interrupt handling section). The microprocessor INT input should be set to level triggering. Data Transfer acknowledge (Motorola Mode). Ready (Intel mode). Serial Data Output (Serial Mode). Motorola Mode A Low signal during a databus read operation indicates that the information is valid ...
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... Serial Data Input (Serial Mode). DI Line Length Equalizer (Hardware Mode). DI Host Mode DI This pin acts as data strobe in Motorola mode and as Write Enable in Intel DI mode. In serial mode this pin is used as Serial Data Input. Hardware Mode This pin determines the shape and amplitude of the transmit pulse. Refer to Table 2 ...
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... Receive path Z Disabled Motorola/Intel/Codec Enable Select. Host Mode: When Low, the host interface is configured for Motorola microcontrollers. When High, the host interface is configured for Intel microcontrollers. DI Hardware Mode: DI This pin determines the line encode/decode selection when in un- ipolar mode: When Low, B8ZS/HDB3 encoders/decoders are enabled for T1/E1 respectively ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Pin Assignments and Signal Descriptions (Sheet 10 of 11) Ball # Pin # Symbol PBGA LQFP E13 84 CLKE 2 N/C 100 RESET A6 12, 13, ...
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Table 1. Pin Assignments and Signal Descriptions (Sheet 11 of 11) Ball # Pin # Symbol PBGA LQFP A4, B4, C4, C11 VCC 67, 68, 75, D4, D11, G1, G14, H1, H14 A11, B11 - TVCC ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.0 Functional Description Figure simplified block diagram of the LXT386. The LXT386 is a fully integrated quad line interface unit designed for T1 1.544 Mbps and E1 2.048 Mbps short haul applications. ...
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... Software Reset - Writing to the RES reset register initiates a 1microsecond reset cycle, except in Intel non-multiplexed mode. In Intel non-multiplexed mode, the reset cycle takes 2 microseconds. Please refer to Host mode section for more information. This operation changes all LXT386 registers to their default values. ...
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... The data and timing recovery circuits provide an input jitter tolerance better than required by Pub 62411 and ITU G.823, as shown in Test Specifications, Depending on the options selected, recovered clock and data signals may be routed through the jitter attenuator, through the B8ZS/HDB3/AMI decoder, and may be output to the framer as either bipolar or unipolar data. 24 Figure 33 ...
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Loss of Signal Detector The loss of signal detector in the LXT386 uses a dedicated analog and digital loss of signal detection circuit independent of its internal data slicer comparators and complies to the latest ITU G.775 ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.2.2 Alarm Indication Signal (AIS) Detection The AIS detection is performed by the receiver independent of any loopback mode. This feature is available in host mode only. Because there is no clock in data recovery ...
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Transmitter The four low power transmitters of the LXT386 are identical. Transmit data is clocked serially into the device at TPOS/TNEG in the bipolar mode or at TDATA in the unipolar mode. The transmit clock (TCLK) supplies the input ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.3.1 Transmit Pulse Shaping The transmitted pulse shape is internally generated using a high speed D/A converter. Shaped pulses are further applied to the line driver for transmission onto the line at TTIP and TRING. ...
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Transmit Pulse Shaping The transmitted pulse shape is internally generated using a high speed D/A converter. Shaped pulses are further applied to the line driver for transmission onto the line at TTIP and TRING. The line driver provides a ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.4 Driver Failure Monitor The LXT386 transceiver incorporates an internal power Driver Failure Monitor (DFM) in parallel with TTIP and TRING that is capable of detecting secondary shorts without cable. DFM is available only in ...
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Figure 7. External Transmit/Receive Line Circuitry TVCC TVCC 68μF 68μ 0.1μF 0.1μF 3.3V 3.3V VCC VCC 0.1μF 0.1μF GND GND 1 Common decoupling capacitor for all TVCC and TGND pins. 1 Common decoupling capacitor for all TVCC and ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.6 Jitter Attenuation A digital Jitter Attenuation Loop (JAL) combined with a FIFO provides Jitter attenuation. The JAL is internal and requires no external crystal nor high-frequency (higher than line rate) reference clock. In Host ...
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Figure 8. Jitter Attenuator Loop TPOS RPOSi TNEG RNEGi TCLK RCLKi JASEL0 MCLK Datasheet QUAD T1/E1/J1 Transceiver — LXT386 FIFO64 FIFO IN CK OUT CK DPLL IN OUT JACF TPOSo RPOS TNEGo RNEG TCLK RCLK JASEL0-1 GCR control ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.7 Loopbacks The LXT386 offers three loopback modes for diagnostic purposes. In hardware mode, the loopback mode is selected with the LOOPn pins. In software mode, the ALOOP, DLOOP and RLOOP registers are employed. 3.7.1 ...
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Remote Loopback During remote loopback circuits and output on the TTIP & TRING pins. Note that input signals on the TCLK, TPOS & TNEG pins are ignored during remote loopback. Figure 11. Remote Loopback TCLK TPOS TNEG RCLK RPOS ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.7.4 Transmit All Ones (TAOS) In Hardware mode, the TAOS mode is set by pulling TCLK High for more than 16 MCLK cycles. In software mode, TAOS mode is set by asserting the corresponding bit ...
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G.772 Performance Monitoring The LXT386 can be configured as a quad line interface unit with all channels working as regular transceivers. In applications using only three channels, the fourth channel can be configured to monitor any of the remaining ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.10 Operation Mode Summary Table 4 lists summarizes all LXT386 hardware settings and corresponding operating modes. Table 4. Operation Mode Summary MCLK TCLK LOOP Clocked Clocked Open Clocked Clocked Clocked Clocked Clocked L Open Clocked ...
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... Motorola mode ACK Low signals valid information is on the data bus. During a write cycle a Low signal acknowledges the acceptance of the write data. In Intel mode RDY High signals to the controlling processor that the bus cycle can be completed. While Low the microprocessor must insert wait states. This allows the LXT386 to interface with wait-state capable micro controllers, independent of the processor bus speed ...
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... Intel Interface The Intel interface is selected by asserting the MOT/INTL pin High. The LXT386 supports non- multiplexed interfaces with separate address and data pins when MUX is asserted Low, and multiplexed interfaces when MUX is asserted High. The address is latched in on the falling edge of ALE ...
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Interrupt Handling Interrupt Sources There are three interrupt sources: 1. Status change in the Loss Of Signal (LOS) status register (04H). The LXT386’s analog/digital loss of signal processor continuously monitors the receiver signal and updates the specific LOS status ...
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LXT386 — QUAD T1/E1/J1 Transceiver 3.14 Serial Host Mode The LXT386 operates in Serial Host Mode when the MODE pin is tied to VCC÷2. the SIO data structure. The registers are accessible through a 16 bit word: an 8bit Command/ ...
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Register Descriptions Table 6. Serial and Parallel Port Register Addresses Name Symbol ID Register Analog Loopback ALOOP Remote Loopback RLOOP TAOS Enable TAOS LOS Status Monitor LOS DFM Status Monitor DFM LOS Interrupt Enable LIE DFM Interrupt Enable DIE ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 7. Register Bit Names (Continued) Register Name Sym RW LOS Status Monitor LOS R DFM Status Monitor DFM R LOS Interrupt Enable LIE R/W DFM Interrupt Enable DIE R/W LOS Interrupt Status LIS R ...
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Table 10. Remote Loopback Register, RLOOP (02H) Bit Name 3-0 RL3-RL0 Setting a bit to “1” enables remote loopback for transceivers 3-0 respectively. Table 11. TAOS Enable Register, TAOS (03H) 1 Bit Name Setting a bit to “1” causes a ...
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... Table 18. Software Reset Register, RES (0AH) Bit Name Writing to this register initiates a 1 microsecond reset cycle, except for Intel non- multiplexed mode. When using Intel non-multiplexed host mode, extend cycle time to 2 3-0 RES3-RES0 microseconds. Please refer to Host Mode section for more information. This operation sets all LXT386 registers to their default values ...
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Table 22. Automatic TAOS Select Register, ATS (0EH) 1 Bit Name Setting a bit to “1” enables automatic TAOS generation whenever a LOS condition is 3-0 ATS3-ATS0 detected in the respective transceiver. 7-4 - Write “0” to these positions for ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 24. Pulse Shaping Indirect Address Register, PSIAD (10H) 1 Bit Name The three bit value written to these bits determine the channel to be addressed channel channel 1 0-2 ...
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Table 28. AIS Interrupt Enable Register, AISIE (14H) 1 Bit Name 3-0 AISIE3-AISIE0 Transceiver 3-0 AIS interrupts are enabled by writing a “1” to the respective bit. 7-4 - Write “0” to these positions for normal operation power-up ...
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LXT386 — QUAD T1/E1/J1 Transceiver 5.0 JTAG Boundary Scan 5.1 Overview The LXT386 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access to the interface pins for board testing purposes. In addition to the traditional IEE1149.1 digital ...
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TAP Controller The TAP controller state synchronous state machine controlled by the TMS input and clocked by TCK ( Figure instruction, receiving data, transmitting data idle state. the states represented in Table 30. ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 16. JTAG State Diagram 1 TEST-LOGIC RESET RUN TEST/IDLE 52 1 SELECT- CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- ...
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JTAG Register Description The following paragraphs describe each of the registers represented in 5.4.1 Boundary Scan Register (BSR) The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply ...
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LXT386 — QUAD T1/E1/J1 Transceiver Example 1. Boundary Scan Register – BSR (Sheet Pin I/O Bit # Signal Type LOOP0 I/O LOOP0 I/O LOOP1 I/O LOOP1 I/O LOOP2 I/O LOOP2 I/O ...
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Example 1. Boundary Scan Register – BSR (Sheet Pin I/O Bit # Signal Type Symbol TCLK0 I TPOS0 I TNEG0 I RCLK0 O RPOS0 O RPOS0 N/A - HIZ0 RNEG0 O RNEG0 LOS0 O LOS0 Datasheet QUAD ...
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LXT386 — QUAD T1/E1/J1 Transceiver 5.5 Device Identification Register (IDR) The IDR register provides access to the manufacturer number, part number and the LXT386 revision. The register is arranged per IEEE 1149.1 and is represented in is shifted in LSB ...
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Analog Port Scan Register (ASR) The ASR bit shift register used to control the analog test port at pins AT1, AT2. When the INTEST_ANALOG instruction is selected, TDI connects to the ASR input and TDO connects ...
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LXT386 — QUAD T1/E1/J1 Transceiver 5.5.3 Instruction Register (IR) The bit shift register that loads the instruction to be performed. The instructions are shifted LSB first. Table 33 Table 33. Instruction Register – IR Instruction Code ...
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Test Specifications Note: Table 34 through Table 53 specifications of the LXT386 and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in recommended operating conditions specified in Table 34. Absolute Maximum Ratings ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 35. Recommended Operating Conditions (Sheet Parameter Average Transmitter Power Supply Current Mode 1, 4 Average Digital Power Supply Current Output load at TTIP and TRING Mode TVCC ...
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Table 36. DC Characteristics (Sheet Parameter Input leakage current Tri state leakage current Tri state output current Line short circuit current Input Leakage (TMS, TDI, TRST) 1. Output drivers will output CMOS logic levels into CMOS loads. ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 38. E1 Receive Transmission Characteristics (Sheet Parameter Data decision threshold Data slicer threshold Loss of signal threshold LOS hysteresis Consecutive zeros before loss of signal LOS reset Low limit 1Hz to ...
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Table 39. T1 Transmit Transmission Characteristics (Sheet Parameter Output power @ 772 KHz 2 levels @ 1544 KHz 51kHz to 102 kHz Transmit return 102 kHz to 2.048 MHz 1 loss 2.048 MHz to 3.072 MHz Bipolar ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 41. Jitter Attenuator Characteristics Parameter JACF = 0 E1 jitter attenuator 3dB corner frequency, host 1 mode JACF = 1 JACF = 0 T1 jitter attenuator 3dB corner frequency, host 1 mode JACF = ...
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Table 42. Analog Test Port Characteristics Parameter 3 dB bandwidth Input voltage range Output voltage range Table 43. Transmit Timing Characteristics Parameter E1 Master clock frequency T1 Master clock tolerance Master clock duty cycle E1 Output pulse width T1 E1 ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 44. Receive Timing Characteristics Parameter Clock recovery capture range 1 Receive clock duty cycle 1 Receive clock pulse width Receive clock pulse width Low time Receive clock pulse width High time 4 Rise/fall time ...
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... J-CLK rising to J-TMS/L-TDI hold time J-TCLK falling to J-TDO valid Figure 20. JTAG Timing TCK TMS TDI TDO Table 46. Intel Mode Read Timing Characteristics 2 Parameter Address setup time to latch Valid address latch pulse width Latch active to active read setup time Chip select setup time to active read ...
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... LXT386 — QUAD T1/E1/J1 Transceiver Figure 21. Non-Multiplexed Intel Mode Read Timing ALE (pulled High INT Tristate RDY 68 tSAR ADDRESS tSCSR tVRD tPRD DATA OUT tDRDY tVRDY tHAR tHCSR tZRD tINT tDRDY tRDYZ Tristate Datasheet ...
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... ADDRESS AD7-AD0 INT tDRDY Tristate RDY Table 47. Intel Mode Write Timing Characteristics (Sheet Parameter Address setup time to latch Valid address latch pulse width Latch active to active write setup time Chip select setup time to active write Chip select hold time from inactive write ...
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... LXT386 — QUAD T1/E1/J1 Transceiver Table 47. Intel Mode Write Timing Characteristics (Sheet Parameter Valid write signal pulse width Inactive write to inactive INT delay time 3 Chip select to RDY delay time Active ready Low time 3 Inactive ready to tri-state delay time 1. Typical figures are and are for design aid only; not guaranteed and not subject to production testing. ...
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... Figure 24. Multiplexed Intel Mode Write Timing ALE tVL CS WR tSALW AD7-AD0 ADDRESS INT tDRDY Tristate RDY Table 48. Motorola Bus Read Timing Characteristics 2 Parameter Address setup time to address or data strobe Address hold time from address or data strobe Valid address strobe pulse width ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 25. Non-Multiplexed Motorola Mode Read Timing A4-A0 ADDRESS tSAR AS (pulled High) tSRW R D7-D0 INT ACK 72 tHAR tSCS tVDS tPDS DATA OUT tDACKP tPACK tHRW tHCS tDZ tINT tDACK Datasheet ...
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Figure 26. Multiplexed Motorola Mode Read Timing AS tSRW R/W CS tASDS DS tSAR D7-D0 ADDRESS INT ACK Table 49. Motorola Mode Write Timing Characteristics (Sheet Parameter Address setup time to address strobe Address hold time ...
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LXT386 — QUAD T1/E1/J1 Transceiver Table 49. Motorola Mode Write Timing Characteristics (Sheet Parameter Data strobe inactive to address strobe inactive delay Active data strobe to ACK output enable time DS asserted to ACK asserted delay ...
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Figure 28. Multiplexed Motorola Mode Write Timin AS tSRW R/W CS tASDS DS tSAS D7-D0 ADDRESS INT ACK Table 50. Serial I/O Timing Characteristics Parameter Rise/fall time any pin SDI to SCLK setup time SCLK to SDI hold time ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 29. Serial Input Timing SCLK t DC LSB SDI Figure 30. Serial Output Timing CLKE = SCLK CS SDO CLKE = ...
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Table 52. G.703 2.048 Mbit/s Pulse Mask Specifications Parameter Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio of positive and negative pulse amplitudes at center of pulse Ratio of positive and negative pulse ...
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Figure 32. T1, T1.102 Mask Templates -0.80 -0.60 -0.40 -0.20 1.20 1.00 0.80 0.60 0.40 0.20 0.00 0.00 0.20 0.40 -0.20 -0.40 -0.60 Tim e [UI] 0.60 0.80 1.00 1.20 ...
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Figure 33. LXT386 Jitter Tolerance Performance 1000 UI 100 4.9 Hz AT&T 62411, Dec 1990 (T1 1 GR-499-CORE, Dec 1995 (T1 Datasheet ...
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LXT386 — QUAD T1/E1/J1 Transceiver Figure 34. Jitter Transfer Performance E1 -10 dB -20 dB -30 dB -40 dB - 3Hz 0 40Hz =2.5 Hz ...
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Figure 35. Output Jitter for CTR12/13 applications 0.2 0.15 0.1 0. 100 Hz 6.1 Recommendations and Specifications AT&T Pub 62411 ANSI T1.102 - 199X Digital Hierarchy Electrical Interface ANSI T1.231 -1993 Digital Hierarchy Layer 1 ...
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LXT386 — QUAD T1/E1/J1 Transceiver 7.0 Mechanical Specifications Figure 36. 60 Plastic Ball Grid Array (PBGA) Package Dimensions 160 PBGA Package • Part Number LXT386BE • Extended Temperature Range (-40 15.00 13.00 ±0.20 4.72 ±0.10 PIN #A1 CORNER PIN #A1 ...
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Figure 37. 100 Pin Low Quad Flat Packages (LQFP) Dimensions 100 Pin LQFP • Part Number LXT386LE • Extended Temperature ° ° Range (- 16.00 BSC 14.00 BSC 12.00 BSC 1.60 0.05 min max 1.40 ±0.05 ...
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... Figure 38. Sample LQFP Non-RoHS Package - Intel Pin 1 Figure 39 shows a sample LQFP RoHS package for the LXT386 Transceiver. Figure 39. Sample LQFP RoHS Package - Intel Pin 1 84 ® LXT386 Transceiver LXT386LE B2 ...
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... DJLXT386LE.B2 WJLXT386LE.B2 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Package Pin RoHS Type Count Compliant B2 LQFP 100 No B2 LQFP 100 Yes Figure Figure 38, “Sample LQFP Non-RoHS Package - Intel® LXT386 Transceiver” Figure 39, “Sample LQFP RoHS Package - Intel® LXT386 Transceiver” 85 ...
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... B = BGA C = CBGA E = TBGA K = HSBGA (BGA with heat slug Product Code xxxxx = 3-5 Digit alphanumeric IXA Product Prefix LXT = PHY layer device IXE = Switching engine IXF = Formatting device (MAC/Framer) IXP = Network processor Intel Package Designator Pb-Free Package Leaded WB HQFP HB WJ LQFP DJ BJ ...