PDLXT300ZNE.F4 Intel, PDLXT300ZNE.F4 Datasheet
PDLXT300ZNE.F4
Specifications of PDLXT300ZNE.F4
Related parts for PDLXT300ZNE.F4
PDLXT300ZNE.F4 Summary of contents
Page 1
... Digital Transmit Driver Monitor Digital Receive Monitor with Loss of Signal (LOS) output and first mark reset Receiver jitter tolerance 0.4 UI from 40 kHz to 100 kHz Microprocessor controllable (LXT300Z only) Compatible with most popular PCM framers Available in 28-pin DIP or PLCC Order Number: 249066-001 January 2001 ...
Page 2
... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
Page 3
Contents 1.0 Pin Assignments and Signal Descriptions 2.0 Functional Description 2.1 Power Requirements............................................................................................. 9 2.1.1 Reset Operation (LXT300Z and LXT301Z) ..............................................9 2.2 Receiver ..............................................................................................................10 2.2.1 Receive (Loss of Signal) Monitor ...........................................................11 2.2.2 Jitter Attenuation (LXT300Z Only)..........................................................11 2.3 Transmitter ..........................................................................................................11 2.3.1 ...
Page 4
LXT300Z/LXT301Z — Advanced T1/E1 Short-Haul Transceivers Figures 1 LXT300Z/LXT301Z Block Diagram ....................................................................... 5 2 LXT300 Pin Assignments and Package Markings ................................................ 6 3 LXT301Z Block Diagram ..................................................................................... 10 4 50% AMI Coding ................................................................................................. 13 5 LXT300Z Serial Interface Data Structure ...
Page 5
Figure 1. LXT300Z/LXT301Z Block Diagram MODE TPOS HOS H/W TNEG T EC1 TCLK INT EC2 SDI EC3 SDO RLOOP MCLK CS LLOOP SCLK TAOS XTALIN XTALOUT RCLK RPOS RNEG LOS DPM Datasheet Advanced T1/E1 Short-Haul Transceivers — LXT300Z/LXT301Z Control Equalizer ...
Page 6
LXT300Z/LXT301Z — Advanced T1/E1 Short-Haul Transceivers 1.0 Pin Assignments and Signal Descriptions Figure 2. LXT300 Pin Assignments and Package Markings 1 28 MCLK 2 27 TCLK 3 26 TPOS 4 25 TNEG 5 24 MODE 6 23 RNEG 7 22 ...
Page 7
Table 1. Pin Descriptions 1 Pin # Sym I/O Master Clock. A 1.544 or 2.048 MHz clock input used to generate internal clocks. Upon Loss of Signal (LOS), RCLK is derived from MCLK. 1 MCLK DI LXT300Z Only: If MCLK ...
Page 8
LXT300Z/LXT301Z — Advanced T1/E1 Short-Haul Transceivers Table 1. Pin Descriptions (Continued) 1 Pin # Sym I/O 19 RTIP AI Receive Tip; Receive Ring. The AMI signal received from the line is applied at these pins. A center-tapped, center-grounded, 2:1 step-up ...
Page 9
Functional Description The LXT300Z and LXT301Z are fully integrated PCM transceivers for both 1.544 Mbps (DSX-1) and 2.048 Mbps (E1) applications. Both transceivers allow full-duplex transmission of digital data over existing twisted-pair or coax installations. The first page of ...
Page 10
LXT300Z/LXT301Z — Advanced T1/E1 Short-Haul Transceivers Figure 3. LXT301Z Block Diagram EC1, EC2, EC3 TPOS Equalizer TNEG Synchronizer TCLK Internal Clock MCLK Generator RCLK RPOS RNEG LOS DPM 2.2 Receiver The LXT300Z and LXT301Z receivers are identical except for the ...
Page 11
Receive (Loss of Signal) Monitor The receive monitor generates a Loss of Signal (LOS) output upon receipt of 175 consecutive zeros (spaces). The receiver monitor loads a digital counter at the RCLK frequency. The count is incremented each time ...
Page 12
LXT300Z/LXT301Z — Advanced T1/E1 Short-Haul Transceivers 2.3.2 Line Code The LXT300Z and LXT301Z transmit data as a 50% AMI line code as shown in consumption is reduced by activating the AMI line driver only to transmit a mark. The output ...
Page 13
Figure 4. 50% AMI Coding TTIP TRING Table 2. LXT300Z Serial Data Output Bits (See Figure 5) Bit Bit Bit ...
Page 14
LXT300Z/LXT301Z — Advanced T1/E1 Short-Haul Transceivers Table 4. Equalizer Control Inputs EC3 EC2 EC1 Line length from transceiver ...
Page 15
Figure 5. LXT300Z Serial Interface Data Structure CS SCLK ADDRESS / COMMAND BYTE R SDI/ SDO ADDRESS / 0 0 COMMAND R/W A0 BYTE CLEAR INTERRUPTS INPUT DATA LOS DFM D0 (LSB) BYTE Datasheet Advanced T1/E1 Short-Haul ...
Page 16
... Figure 6 shows a typical 1.544 Mbps T1 application. The LXT300Z is configured in the Host mode with a typical T1/ESF framer providing the digital interface with the host controller. Both devices are controlled through the serial interface. The LXP600A Clock Adapter (CLAD) provides the 2.048 MHz system backplane clock, locked to the recovered 1.544 MHz clock signal. The power supply inputs are tied to a common bus with appropriate decoupling capacitors installed (68 µ ...
Page 17
... LXT300Z Hardware Mode E1 Interface Application Figure 7 shows a typical 2.048 Mbps E1 application. The LXT300Z is configured in Hardware mode with a typical E1/CRC4 framer. Resistors are installed in line with the transmit transformer for loading a 75 coaxial cable. The in-line resistors are not required for transmission on 120 shielded twisted-pair lines ...
Page 18
... The hard-wired control lines for TAOS, LLOOP and RLOOP are individually controllable, and the LLOOP and RLOOP lines are also tied to a single control for the Reset function Figure 7. Typical LXT300Z 75 E1/CRC4 FRAMER NOTE 2 TCLK TPOS TNEG RNEG ...
Page 19
... Figure 8 shows a typical 1.544 Mbps T1 application of the LXT301Z. The LXT301Z is shown with a typical T1/ESF framer. The LXP600A Clock Adapter (CLAD) provides the 2.048 MHz system backplane clock, locked to the recovered 1.544 MHz clock signal. The power supply inputs are tied to a common bus with appropriate decoupling capacitors installed (68 µF on the transmit side, 1.0 µ ...
Page 20
... LXT301Z 2.048 Mbps E1 Interface Application Figure 9 shows a typical 2.048 Mbps E1 application of the LXT301Z. The LXT301Z is shown with a typical E1/CRC4 framer. Resistors are installed in line with the transmit transformer for loading a 75 coaxial cable. The in-line resistors are not required for transmission on 120 twisted-pair lines ...
Page 21
Test Specifications Note: Table 6 through Table 13 of the LXT300Z/301Z and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in operating conditions specified in Table 6. Absolute Maximum Ratings Parameter DC ...
Page 22
LXT300Z/LXT301Z — Advanced T1/E1 Short-Haul Transceivers Table 9. Analog Characteristics Parameter DSX-1 AMI output pulse amplitudes E1 (120 E1 (75 Transmit amplitude variation with supply Recommended output load at TTIP and TRING 2 Driver output impedance ...
Page 23
Figure 10. LXT300Z Typical Receive Jitter Tolerance 10000 UI 1200 UI 1000 UI 138 UI 100 1 0.4 UI 0 Datasheet Advanced T1/E1 Short-Haul Transceivers — LXT300Z/LXT301Z ...
Page 24
LXT300Z/LXT301Z — Advanced T1/E1 Short-Haul Transceivers Figure 11. LXT300Z Typical Receive Jitter Transfer Performance -10 dB -20 dB -30 dB Typical LXT300Z Performance - Table 10. ...
Page 25
Figure 12. LXT300Z Receive Clock Timing Diagram t RCLK t RPOS RNEG RPOS RNEG Table 11. LXT301Z Receive Timing Characteristics (See Figure 13) Parameter DSX-1 2 Receive clock duty cycle DSX-1 2 Receive clock pulse width DSX-1 Receive clock pulse ...
Page 26
LXT300Z/LXT301Z — Advanced T1/E1 Short-Haul Transceivers Figure 13. LXT301Z Receive Clock Timing Diagram RCLK RPOS RNEG Table 12. LXT300Z/301Z Master Clock and Transmit Timing Characteristics (See Figure 14) Parameter DSX-1 Master clock frequency Master clock tolerance Master clock duty cycle ...
Page 27
Table 13. LXT300Z Serial I/O Timing Characteristics (See Figure 15 and Figure 16) Parameter Rise/fall time - any digital output SDI to SCLK setup time SCLK to SDI hold time SCLK Low time SCLK High time SCLK rise and fall ...
Page 28
LXT300Z/LXT301Z — Advanced T1/E1 Short-Haul Transceivers Figure 16. LXT300Z Serial Data Output Timing Diagram CS SCLK t CDV SDO CLKE=1 t CDV SDO CLKE CDZ t CDZ HIGH Z HIGH Z Datasheet ...
Page 29
Mechanical Specifications Figure 17. Package Specifications 28-pin Plastic Dual In-Line Package • Extended Temperature Range (-40 ° °C) • Part Number LXT300ZNE • Part Number LXT301ZNE 28-pin Plastic Leaded Chip Carrier • ...
Page 30
...