TXC-03305AIPQ Transwitch Corporation, TXC-03305AIPQ Datasheet
TXC-03305AIPQ
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TXC-03305AIPQ Summary of contents
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... DS3 Transmit Clock and Data Microprocessor Copyright 2000 TranSwitch Corporation M13X is a trademark of TranSwitch Corporation TranSwitch and TXC are registered trademarks of TranSwitch Corporation TranSwitch Corporation Tel: 203-929-8810 DS3/DS1 MUX/DEMUX, Enhanced Features DESCRIPTION The M13X CMOS VLSI device provides the functions needed to multiplex and demultiplex 28 independent DS1 signals to and from a DS3 signal with either an M13 or C-bit frame format ...
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... Department to receive relevant updated and supplemental documentation issued. They should also contact the Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. TXC-03305-MB Ed. 4, September 2000 DATA SHEET TABLE OF CONTENTS ...
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... DS1 Interface Jitter Transfer Limits ................................................................. 46 23DS1 to DS1 Jitter Transfer Limits ................................................................................ 47 24HDLC Format .............................................................................................................. 50 25Boundary Scan Schematic .......................................................................................... 58 26Example Channelized T3 Application .......................................................................... 95 27M13X TXC-03305 208-Lead Plastic Ball Grid Array Package .....................................96 28M13X TXC-03305 208-Lead Plastic Quad Flat Package ............................................ 97 DATA SHEET LIST OF FIGURES - 3 - M13X TXC-03305 Page TXC-03305-MB Ed ...
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... TXC-03305-MB Ed. 4, September 2000 DATA SHEET 7 1 DS3 DS2 Sync/Destuff Alarm/Status Control 7 1 DS2 Framing/Stuffing Test Access Port TMS TDI TDO TCK TRS Figure 1. M13X TXC-03305 Block Diagram - 4 - DR28 28 DR1 1 DS1 CR28 Outputs CR1 DS1 Micro- Local processor Loopbacks Micro- Interface ...
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... Plastic Ball Grid Array (PBGA) package or a 208-lead Plastic Quad Flat Package (PQFP). The PQFP version is intended to be used as a replacement for TranSwitch’s M13E device (TXC-03303-AIPQ) and is not recommended for new designs. The PBGA version is intended for new designs. ...
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... C18, C19, C20, C21). The receive C-bit interface consists of a serial data output (CDR), an output clock (CCKR), a data link indicator pulse (CDCCR), and an output framing pulse (CFMR). The data link indicator pulse identifies the location of the three data link C-bits, C13, C14, and C15. TXC-03305-MB Ed. 4, September 2000 DATA SHEET ...
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... C1 = C-bit parity mode C2 = Reserved C3 = Far End Alarm and Control (FEAC) Not defined, set to 1 C-bit Parity bits Far End Block Error (FEBE) Maintenance data link (28 kbit/s) Not defined, set to 1 Not defined, set to 1 Figure 2. C-Bit Assignments - 7 - M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
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... Note: This a bottom view of the M13X 208-lead plastic ball grid array package. All leads are solder balls. Some lead symbols may be abbreviated. See Figure 27 for package dimension information. This diagram is rotated relative to the bottom view shown in Figure 27. Figure 3. M13X TXC-03305 Lead Diagram for PBGA Package TXC-03305-MB Ed. 4, September 2000 ...
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... GND Note: This a top view of the M13X 208-lead plastic quad flat package. Some lead symbols may be abbreviated. See Figure 28 for package dimension information. Figure 4. M13X TXC-03305 Lead Diagram for PQFP Package DATA SHEET M13X TXC-03305AIPQ Lead Diagram - 9 - M13X TXC-03305 GND SCAN_EN ...
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... G15, K3, 155, 158 K15, N6, R7, T2, T7 Notes for lead descriptions tables Input Output Power ** See Input, Output and Input//Output Parameters section below for Type definitions. TXC-03305-MB Ed. 4, September 2000 DATA SHEET I/O/P* Type** P VDD: +5-volt supply voltage, 5%. P Ground: 0 volts reference. ...
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... During cer- tain DS3 alarm conditions (programmable via 1TAIS1 and 1TAIS0, bits 5 and 4 in register 20H) the M13X provides a DS1 clock signal for clocking out AIS which is derived from the XCK clock lead M13X TXC-03305 Name/Function TXC-03305-MB Ed. 4, September 2000 ...
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... DR26 B5 199 DR27 B4 202 6 DR28 C2 TXC-03305-MB Ed. 4, September 2000 DATA SHEET I/O/P Type O TTL2mA Receive DS1 Data, Channels 1 - 28: Demulti- plexed DS1 channels. The first DS1 channel corre- sponds to DR1, while the last DS1 channel corresponds to DR28. During normal operation these data outputs are stretched due to overhead and stuff bit removal ...
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... M13X on either the rising or falling edges of these clocks, depending on the set- ting of the INVCK bit. The clock for the first DS1 channel corresponds to CT1, while the clock for the last DS1 channel corresponds to CT28 M13X TXC-03305 Name/Function TXC-03305-MB Ed. 4, September 2000 ...
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... DT24 M14 118 DT25 T14 96 DT26 T15 98 DT27 R15 100 109 DT28 R16 TXC-03305-MB Ed. 4, September 2000 DATA SHEET I/O/P Type I TTL Transmit DS1 Data, Channels 1 - 28: The first DS1 channel corresponds to DT1, while the last DS1 channel corresponds to DT28 Name/Function ...
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... DS3 clock (XCK or DS3CR), and is used to align the transmit DS3 frame. The X1 bit of the transmit DS3 frame is three clocks delayed with respect to the TXFRM. The use of this lead is optional not used then it must either be left floating or pulled high M13X TXC-03305 Name/Function TXC-03305-MB Ed. 4, September 2000 ...
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... M13X TXC-03305 MICROPROCESSOR INTERFACE Lead No. Lead No. Symbol BGA PQFP P1 A15 161 P0 B14 162 TXC-03305-MB Ed. 4, September 2000 DATA SHEET I/O/P Type I TTLp Microprocessor Interface Type Select: The type of microprocessor interface selected by these two bits is given in the table below: P1 High High High ...
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... Multiplexed - These bidirectional leads constitute address/data buses for accessing the M13X registers. Intel/Motorola - These bidirectional leads are used only for transferring data. The most significant bit is A/ TXC-03305 Name/Function 6 Register Address 6 5 Register M13X Address TXC-03305-MB Ed. 4, September 2000 M13X ...
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... RD/WR ALE RDY/ A14 163 DTACK INT/IRQ B1 4 TXC-03305-MB Ed. 4, September 2000 DATA SHEET I/O/P Type I TTL Select: A low enables data transfers between the microprocessor and the M13X registers during a read/ write bus cycle. I TTL Read (Intel/Multiplexed) or Read/Write (Motorola): Intel/Multiplexed - An active low signal generated by the microprocessor for reading the M13X register locations ...
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... M13E device applications. This signal is not needed if the internal HDLC controller is used since the C13, C14, and C15 C-bits are then processed internally. This signal is enabled by placing a high on the DLEN input signal lead M13X TXC-03305 Name/Function TXC-03305-MB Ed. 4, September 2000 ...
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... CCKT R12 92 CDT N12 89 CFMT T12 91 CDCCT A5 198 TXC-03305-MB Ed. 4, September 2000 DATA SHEET I/O/P Type O TTL8mA Transmit C-Bit Clock: A gapped clock signal is provided for clocking in selected transmit C-bit data (CDT). Data is clocked into the M13X on the rising edges of CCKT. I TTL ...
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... M13X monitors this clock for transitions. When a clock failure is detected, the M13X automatically switches to the receive clock (DS3CR) for multiplexer and microprocessor operation. Receive loop timing (a 1 written to bit 3, LPTIME, in 02H) also causes the receive clock to become the transmit clock M13X TXC-03305 Name/Function Name/Function TXC-03305-MB Ed. 4, September 2000 ...
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... SCAN TEST LEADS Lead No. Symbol BGA MTEST K2 SCAN_EN R10 SCAN_SHIFT B15 TXC-03305-MB Ed. 4, September 2000 DATA SHEET I/O/P Type I TTLp Test Mode Select: The signal present on this lead is used to control boundary scan test operations. This lead is provided with an internal pull-up resistor. ...
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... Note 1 Level per EIA/JEDEC JESD22-A112 Note 2 100 % non-condensing V Note 3 Meets JEDEC JC-40.2 Unit Test Conditions o C/W 0 ft/min linear airflow o C/W 0 ft/min linear airflow Unit Test Conditions Inputs switching and worst case process and loading. TXC-03305-MB Ed. 4, September 2000 M13X ...
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... Parameter Input leakage current Input capacitance INPUT PARAMETERS FOR TTLp Parameter Input leakage current Input capacitance Note: The TTLp input has a 50k (nominal) internal pull-up resistor. TXC-03305-MB Ed. 4, September 2000 DATA SHEET Min Typ Max DD 0 Min Typ Max 2.0 0.8 ...
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... M13X TXC-03305 Unit Test Conditions 4.75 -2 4.75 2 LOAD LOAD 5.25 DD Unit Test Conditions V 4.75 <V < 5. 4.75 <V < 5. 5.25; DD Input = 0 to 5.25V 4.75 -8 4.75 8 LOAD LOAD LOAD LOAD 5.25 DD TXC-03305-MB Ed. 4, September 2000 ...
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... DS3CR clock period DS3CR duty cycle ( PWH CYC DS3DR setup time before DS3CR DS3DR hold time after DS3CR TXC-03305-MB Ed. 4, September 2000 DATA SHEET /2 for CMOS input signals or 1.4 V for all TTL input and output signals. DD Figure 5. DS3 Receive Timing t CYC ...
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... TXFRM setup time before XCK/DS3CR TXFRM hold time after XCK/DS3CR DATA SHEET Figure 6. DS3 Transmit Timing t CYC t PWH CYC t PWH t OD(1) X1 Symbol Min t 20 CYC / PWH CYC t 2.0 OD(1) t 5.0 OD( M13X TXC-03305 t OD(2) Typ Max Unit 22. 8 TXC-03305-MB Ed. 4, September 2000 ...
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... CRn clock period CRn high time CRn low time DRn output delay after CR Note: When the DJBS are enabled, the DS1 receive timing is derived from the transmit clock source, which can be DS3CR or XCK. TXC-03305-MB Ed. 4, September 2000 DATA SHEET PWL Symbol Min ...
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... CTn clock period Max indicates the ability of the device to accept a gapped clock but does not indicate a continuous period. DATA SHEET Figure 9. DS1 Transmit Timing t CYC t t PWH PWL Symbol Min t 583 CYC t 145 PWH t 145 PWL M13X TXC-03305 Typ Max Unit 648 1305 ns 324 -- ns 324 -- and t are SU H TXC-03305-MB Ed. 4, September 2000 ...
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... CFMR (Output) Parameter CCKR clock period CCKR output delay after CFMR CDR output delay after CCKR CCKR delay after CDCCR CDCCR delay after CCKR CFMR pulse width (high) TXC-03305-MB Ed. 4, September 2000 DATA SHEET Figure 10. C-Bit Receive Interface Timing t CYC C13 C14 ...
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... CDCCT delay after CCKT CFMT pulse width DATA SHEET t CYC C5 C6 C13 C14 C15 t D(1) Symbol Min t CYC D( M13X TXC-03305 C16 C17 C18 C19 C20 C21 t D(2) Typ Max Unit 3800 3800 ns 1900 ns 3800 ns 1900 ns TXC-03305-MB Ed. 4, September 2000 ...
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... The RDY/DTACK output lead is always driven high when the SEL lead is low, otherwise it is tri-stated, which corresponds to the behavior of the M13E device. 2. The SEL lead must be brought high for 2 transmit clock cycles before the start of a new read cycle. TXC-03305-MB Ed. 4, September 2000 DATA SHEET ...
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... The SEL lead must be brought high for 2 transmit clock cycles before the start of a new write cycle. DATA SHEET t H(1) Data PW(2) t W(2) Symbol Min t 95 PW 200 PW( W( M13X TXC-03305 t W(1) t H(2) Typ Max Unit 212,000 ns ns TXC-03305-MB Ed. 4, September 2000 ...
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... The RDY/DTACK output lead is always driven high when the SEL lead is low, otherwise it is tri-stated, which corresponds to the behavior of the M13E device. 2. The SEL lead must be brought high for 2 transmit clock cycles before the start of a new read cycle. TXC-03305-MB Ed. 4, September 2000 DATA SHEET ...
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... M13E device. 2. The SEL lead must be brought high for 2 transmit clock cycles before the start of a new write cycle. DATA SHEET t SU(2) t SU( Symbol Min Typ t 0.0 H( SU( SU( H( SU( M13X TXC-03305 t H(1) t H(2) Max Unit 212,000 ns TXC-03305-MB Ed. 4, September 2000 ...
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... DTACK float time after SEL Note: The transmit clock (XCK) or receive clock (DS3CR) must be present for the microprocessor bus interface to operate. The DTACK signal lead has the same functional timing as the M13E device when the M13X lead is high. TXC-03305-MB Ed. 4, September 2000 DATA SHEET t ...
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... The DTACK signal lead has the same functional timing as the M13E device when the M13X lead is high. DATA SHEET t t SU(1) t PW(1) t SU(3) t PW( Symbol Min t 0.0 H( SU( SU(2) t 5.0 H( PW( SU(3) t 0.0 H( PW( TXC-03305 t H(1) t H(2) SU( Typ Max 212,000 60 100 20 TXC-03305-MB Ed. 4, September 2000 M13X Unit ...
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... TCK clock low time TMS setup time before TCK TMS hold time after TCK TDI setup time before TCK TDI hold time after TCK TDO delay from TCK TRS pulse width TXC-03305-MB Ed. 4, September 2000 DATA SHEET Figure 18. Boundary Scan Timing t PWH t ...
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... Regardless of the setting of the M13X lead, the M13XID0 bit (register 10H, bit 7) bit will always be set to 0. The 1. Saturate, as used throughout this document when referring to a counter, means that a counter stops at its maximum count and does not roll over to zero when the next count event occurs. DATA SHEET 1 when a count of FFFFH M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
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... Figure 19 shows the functional architecture of the resets in the M13X device. Please note that this diagram rep- resents functionality and not necessarily implementation. HRESET Lead TRS Lead Note: Low corresponds to logic 0 in this diagram. TXC-03305-MB Ed. 4, September 2000 DATA SHEET Active Low Signal Software Reset Reset for system logic (active low) ...
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... The M13X meets and exceeds the timing jitter requirements specified in [GR-499] for: • Tolerance ([GR-499] section 7.3.1) • Transfer ([GR-499] section 7.3.2) • Generation ([GR-499] section 7.3.3) • Enhancement ([GR-499] section 7.3.4) DATA SHEET - 41 - M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
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... DS1 signals. The DJBs should be enabled during such a test to ensure that they do not drop data sufficient to only check the RX DS1s for errors, however a more complete, but not required, check should include all of the signals. TXC-03305-MB Ed. 4, September 2000 DATA SHEET 2 ...
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... Jitter Frequency (Hz) Input Jitter Amplitude (UIpp) 10 18.564 40 9.814 100 7.314 400 6.064 1000 5.861 4000 2.423 10000 1.134 40000 0.556 - 43 - M13X TXC-03305 DS1 Jitter Tolerance Mask to GR-499-CORE 40,000 8,000 10,000 100,000 TXC-03305-MB Ed. 4, September 2000 ...
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... M13X TXC-03305 100 10 1.0 0.3 0.1 1.0 10 Jitter Frequency (Hz) TXC-03305-MB Ed. 4, September 2000 DATA SHEET slope = -20 dB/decade 600 669 100 1,000 Jitter Frequency (Hz) Input Jitter Amplitude (UIpp) 10 <64 100 <64 600 <64 1,000 <64 10,000 <64 30,000 59.438 100,000 17.139 400,000 2 ...
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... UI input jitter applied. The generated jitter is well within the 1.0 UI spec at 15 KHz. The GR-499-CORE section 7.3.2 states that at such frequencies, the jitter transfer can- not be measured. DATA SHEET - 45 - M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
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... M13X TXC-03305 0.1 0 -10 -20 -30 -34.05 -40 -49.61 -50 -60 1.0 10 Figure 22. DS3 to DS1 Interface Jitter Transfer Limits TXC-03305-MB Ed. 4, September 2000 DATA SHEET slope = -40 dB/decade Measured for M13X 350 2500 100 1,000 Jitter Frequency (Hz) Jitter Frequency (Hz) Jitter Gain (dB) 10 100 1,000 14,000 ...
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... Jitter Frequency (Hz) Jitter Gain (dB) 10 0.07 40 -8.16 100 -15.72 350 -27.42 1,000 -37.00 2,500 -44.71 15,000 -40. M13X TXC-03305 slope = -20 dB/decade Exceeds measurement limits at 15,000 HZ See Note in “JITTER TRANSFER” section 15,000 10,000 100,000 TXC-03305-MB Ed. 4, September 2000 ...
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... M13X is about 0.30 UIpp and 0.038 UIrms over a 10Hz - 40 KHz jitter frequency range and about 0.028 UIpp and 0.014 UIrms over an 8 KHz - 40 KHz jitter frequency range for all DS1 and DS3 clock offset fre- quencies. TXC-03305-MB Ed. 4, September 2000 DATA SHEET ...
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... RX PMDL MESSAGE LENGTH register (39H), the RX PMDL FIFO DEPTH register (3AH), and at least one byte from the RX PMDL FIFO interface register (38H) are read within 212 s before they can be updated by the next PMDL byte. DATA SHEET Description - 49 - M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
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... The M13X is able to successfully delineate HDLC-encapsulated PMDL messages in this case. An 80-byte PMDL FIFO is provided in the transmit direction to allow at least one complete message to be stored for processing. A 159-byte PMDL FIFO is provided in the receive direction, which permits at least two TXC-03305-MB Ed. 4, September 2000 DATA SHEET 7 ...
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... This setting of RHIE is used when the message is expected to be longer than 159 bytes. DATA SHEET mask bits MIRRHIS(2-0) should be set to 110, but - 51 - M13X TXC-03305 the octet. The HDLC TXC-03305-MB Ed. 4, September 2000 ...
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... Transmit frames in the M13X are exempt from checking, since the transmit PMDL data are written into the transmit PMDL FIFO as octets. Also not expected that the transmit PMDL message stop transmitting on a non-octet boundary. Therefore all transmit PMDL messages will default to an integral number of octets in length, before stuffing. TXC-03305-MB Ed. 4, September 2000 DATA SHEET - 52 - ...
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... The desired message must be written by the microprocessor into the transmit PMDL FIFO by writing each byte in turn into the TX PMDL FIFO register in register 37H. Bit 0 represents the first bit in the byte to be transmitted. DATA SHEET - 53 - M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
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... RX PMDL MESSAGE LENGTH register and the interrupt requests read from IRLRHIS(2-0) and IRLRXFS(1- queue. The message boundaries and the validity of the messages read from the FIFO may be determined from interrupt request and message length values. This TXC-03305-MB Ed. 4, September 2000 DATA SHEET ...
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... The high byte of a 16-bit counter is not directly accessible via the microprocessor interface; address 3EH must be used to read its contents. DATA SHEET - 55 - M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
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... CFMR (frame output). The following DS3 C-bits are output at this interface: C2, C3, C4, C5, C6, C13, C14, C15, C16, C17, C18, C19, C20, and C21. Unlike the transmit C-bit interface, all of the indicated C-bits are always available. TXC-03305-MB Ed. 4, September 2000 DATA SHEET ...
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... When the SAMPLE/PRELOAD instruction is shifted in, the M13X device remains fully operational. While in this test mode, M13X input data, and data destined for device outputs, can be captured and shifted out for inspec- tion. The data is captured in response to control signals sent to the TAP controller. DATA SHEET - 57 - M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
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... TDI input, through an internal scan cell, to the TDO lead. The purpose of this instruction is to abbreviate the scan path through the circuits that are not being tested to only a single clock delay. TXC-03305-MB Ed. 4, September 2000 DATA SHEET ...
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... DATA SHEET Default Value 0000 Revision of the M13X (0 H) 0000 1100 1110 1001 M13X Part # (03305 = 0CE9 H) 000 0110 1011 M13X Manufacturer’s ID (TranSwitch = Required bit - 59 - M13X TXC-03305 Comment TXC-03305-MB Ed. 4, September 2000 ...
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... I 182 153 -- -- 152 O 184 151 O 185 150 O 186 Note: The comments column indicates the functional operation of the corresponding lead. TXC-03305-MB Ed. 4, September 2000 DATA SHEET Lead No. Symbol PBGA C16 TDI [SCAN Input] A15 P1 Input B14 P0 Input -- -- Tri-State control for cell 173. ...
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... M13X Input -- -- Tri-State control for cell 129 Tri-state. B1 INT/IRQ Output3 C2 DR28 Output3 D2 CR28 Output3 D3 DR19 Output3 D1 CR18 Output3 D4 DR18 Output3 E2 CR17 Output3 E1 DR17 Output3 E3 CR16 Output3 E4 DR16 Output3 F2 CR15 Output3 F1 DR15 Output3 F3 CR14 Output3 - 61 - M13X TXC-03305 Comments TXC-03305-MB Ed. 4, September 2000 ...
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... Note: The comments column indicates the functional operation of the corresponding lead. TXC-03305-MB Ed. 4, September 2000 DATA SHEET Lead No. Symbol PBGA G2 DR14 Output3 G1 CR13 Output3 G3 DR13 Output3 G4 CR12 Output3 H2 DR12 Output3 H1 CR11 Output3 H3 DR11 Output3 H4 CR10 Output3 J4 DR10 Output3 J3 CR9 Output3 J1 DR9 ...
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... Input R9 A/D3 D3 Output3 N10 A/D2 D2 Input N10 A/D2 D2 Output3 P10 A/D1 D1 Input P10 A/D1 D1 Output3 T10 A/D0 D0 Input T10 A/D0 D0 Output3 -- -- Internal. Always set to 1. N11 S7 Input P11 S6 Input T11 S5 Input N12 CDT Input - 63 - M13X TXC-03305 Comments TXC-03305-MB Ed. 4, September 2000 ...
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... I 130 16 I 131 15 I 132 14 I 133 13 I 134 Note: The comments column indicates the functional operation of the corresponding lead. TXC-03305-MB Ed. 4, September 2000 DATA SHEET Lead No. Symbol PBGA P12 XCK Input T12 CFMT Output2 R12 CCKT Output2 P13 DS3DT ...
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... CT9 Input F16 DT9 Input F15 CT10 Input E13 DT10 Input E14 CT11 Input E16 TXFRM Input E15 DT11 Input D15 CT12 Input -- -- Internal. Always set Internal. Always set to 1. C15 TDO [SCAN Output M13X TXC-03305 Comments TXC-03305-MB Ed. 4, September 2000 ...
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... Direction From Receive DS3DR (DJB enabled) Receive DS3DR (DJB disabled) Transmit DTn TXC-03305-MB Ed. 4, September 2000 DATA SHEET F0 Resets internal counters and FIFOs. 00 Presets internal counters and FIFOs. ) leads which provide internal circuit isolation. All Delay (min.) Delay (typ.) Delay (max.) ...
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... DS2OOF3 DS2OOF2 Test Bits TXFS(1-0) TFEAC4 TFEAC3 TFEAC2 RFEAC4 RFEAC3 RFEAC2 LLB21 LLB20 LLB11 1LBV3 1LBV2 1LBV1 R3AIS1 R3AIS0 T3AIS1 TXC-03305-MB Ed. 4, September 2000 M13X Bit 0 XR1 XT M13MODE DS2OOF1 D10 LB1 LB2 LB3 LB4 LOS1 LOS2 LOS3 LOS4 IDL1 IDL2 IDL3 ...
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... R/W DJB R/W Notes: 1. Read/write (R/W); Read -only (R); Read-only - latched register R(L). 2. F0H followed by 00H resets the entire device. TXC-03305-MB Ed. 4, September 2000 DATA SHEET Bit 6 Bit 5 Bit 4 AISCEQ0 Test Bits IRLB25 IRLB21 IRLB17 IRLB26 IRLB22 IRLB18 IRLB27 IRLB23 IRLB19 IRLB28 ...
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... The DS3CR lead is still monitored for this alarm during DS3 local loop- back (control bit 3LBK = 1), so that it may be necessary to set control bits 1TAIS1 and 1TAIS0 prevent AIS insertions into the receive DS1 data stream. This bit position is unlatched M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
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... PBITE 1 CBITE 0 XT TXC-03305-MB Ed. 4, September 2000 DATA SHEET Description Transmit DS3 Clock Failure: A transmit DS3 clock failure alarm occurs, and this bit is set to 1, when the transmit input clock (XCK) is stuck high or low for 6-7 DS3CR clock cycles. A failure causes the receive clock to become the transmit clock ...
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... C1 Value Random All 1s In addition, any C-bit that is received as 0 will increment the C-bit Equal to Zero Counter in register 22H TXC-03305 DS1 Idle Code Selected QRS) including zero Application M13 format C-bit parity format TXC-03305-MB Ed. 4, September 2000 M13X ...
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... CPn (n=7-0) 06 7-0 PPn (n=7-0) TXC-03305-MB Ed. 4, September 2000 DATA SHEET Description DS2 Out of Frame Alarm Indication bits 6-0 corresponds to an Out Of Frame alarm for the corresponding DS2 channel (7-1). A DS2 OOF occurs when two out of four consecutive framing bits are in error. A DS2 OOF for a DS2 channel causes AIS to be inserted into its four DS1 chan- nels when 1TAIS1, 1TAIS0 = register 20H, bits 5 and 4 ...
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... Channel DS3 Notes: For CON/DIS, Connect = 1, Disconnect = 0 For FEAC (C-bit parity mode only DS2 C or stuff bit inversion - 73 - M13X TXC-03305 D11 TXC-03305-MB Ed. 4, September 2000 0 D10 ...
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... LB16 2 LB12 1 LB8 0 LB4 TXC-03305-MB Ed. 4, September 2000 DATA SHEET Description Receive Loopback Requests: Bit 7, LBALL (all DS1 channels), bits 6-0 (LBn), and registers 09H through 0BH indicate the loopback request detected. For the M13 format mode, a loopback request is received when any of the conditions (DS2 C-bit or stuff) are detected five or more times in succession ...
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... IDLn bit, the DS1 channel is looped back instead. The loopback is from the receive to the transmit direction. When the IDLn bit is written with a 0, the DS1 transmit source is from the chan- nel’s DTn/CTn leads M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
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... R3CKF 2 T3CKF 1 XR2 0 XR1 TXC-03305-MB Ed. 4, September 2000 DATA SHEET Description Reserved: This bit should always be written with a 0. Internal DS1 Idle Channel/Loopback: The IDLn bits in this register are used for generating and transmitting a DS1 idle pattern or for setting up a local DS1 loopback for channel n. When register 1EH is written with a code ...
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... PMDL bits) after which they are reset to 0. The priority for detecting these alarms is: • Abort (highest) • Invalid Frame Received • FCS Error Received • Start of Message Indication • Valid Message Received - 77 - M13X TXC-03305 Condition Present TXC-03305-MB Ed. 4, September 2000 ...
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... RXFS0 2-1 TXFS1- TXFS0 0 Reserved 1B 7-0 FMEn (n=7-0) TXC-03305-MB Ed. 4, September 2000 DATA SHEET Description Receive PMDL FIFO Status: The following table lists the various FIFO sta- tus indications associated with the receive PMDL FIFO. RXFS1 RXFS0 0 0 Normal. PMDL FIFO less than half full. ...
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... EXEC bit is set the M13X. • Transmission must be terminated before another FEAC word can be loaded and transmitted. Note: The C3CLKI bit in register 19H must be set this register is used to transmit a FEAC message M13X TXC-03305 1CH TXC-03305-MB Ed. 4, September 2000 ...
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... FIDL 6 NEW 5-0 RFEACn (n=6-1) TXC-03305-MB Ed. 4, September 2000 DATA SHEET Description Receive Single FEAC Word: Bit 7 (FIDL) is the FEAC idle channel indica- tion. It clears whenever bit is received framing the six-bit variable word. Bit 7 cannot be reset by a microprocessor read cycle. Bit 6 (NEW) indicates when a new FEAC word has been detected ...
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... Clear Channel Clear Channel Confirmed Initialization Register: This register location is used to reset and initialize the M13X. After power becomes stable Hex followed Hex must be written into this location TXC-03305 Res. LLB22 LLB21 LLB20 LLB11 LLB10 TXC-03305-MB Ed. 4, September 2000 M13X ...
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... TXC-03305-MB Ed. 4, September 2000 DATA SHEET Description Tri-State DS1 Receive Channels causes all 28 receive DS1 data (DRn) and clock (CRn) output leads to be set to a high impedance state. loss of signal detection selects the transmit DS1 channels for loss of signal detection ...
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... TXC-03305 Framed 1010 pattern C-bits = 0 X-bits disregarded Framed 1010 pattern C-bits = 0 X-bits = 1 Framed 1010 pattern C-bits disregarded X-bits disregarded Undefined - Do not use Unframed 1010 pattern Unframed all ones pattern Undefined - Do not use TXC-03305-MB Ed. 4, September 2000 M13X ...
Page 84
... T3AIS0 22 7-0 C1BZn (n=7-0) 23 7-0 MEn (n=7-0) TXC-03305-MB Ed. 4, September 2000 DATA SHEET Description Transmit DS3 AIS Selection: A DS3 AIS may be generated in one of four ways. The following table selects the DS3 AIS generation mechanism: T3AIS1 T3AIS0 Transmit DS3 AIS Selection 0 0 ...
Page 85
... If the corresponding interrupt request mask bit is set regis- ter 2FH then the INT/IRQ lead goes active to signal an interrupt request to the external microprocessor when a bit in these registers becomes set microprocessor read cycle clears all set interrupt request bits in the regis- ter that is read M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
Page 86
... IRR3CKF 2 IRT3CKF 1 IRXR2 0 IRXR1 TXC-03305-MB Ed. 4, September 2000 DATA SHEET Description New FEAC Message Interrupt Request Bit: The NEW condition is defined as having received a NEW FEAC message. A NEW FEAC mes- sage is understood to have been received when 5 consecutive and identi- cal FEAC messages have been received. The NEW FEAC condition is exited after a NEW FEAC message has been declared ...
Page 87
... C1 Bit Equal to Zero Counter Saturated Interrupt Request: This bit becomes set when the C1 Bit Equal to Zero Counter (22H) saturates. DS3 M-bits in Error Counter Saturated Interrupt Request: This bit becomes set when the DS3 M-Bits in Error Counter (23H) saturates M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
Page 88
... Bit Symbol 2C 7-5 IRRHIS2- IRRHIS0 TXC-03305-MB Ed. 4, September 2000 DATA SHEET Description Receive PMDL Interrupt Request: The following table lists the various interrupt status indications associated with the receive PMDL message. The significance of these bits is controlled by control bit RHIE (bit 5) in reg- ister 3DH ...
Page 89
... If this bit is set and the corresponding interrupt mask bit in register 35H is set then the INT/IRQ lead goes active to signal an interrupt request to the external microprocessor. Reserved: These bits are reserved and must always be ignored M13X TXC-03305 Condition Present Condition Present TXC-03305-MB Ed. 4, September 2000 ...
Page 90
... MIRR3CKF 2 MIRT3CKF 1 MIRXR2 0 MIRXR1 TXC-03305-MB Ed. 4, September 2000 DATA SHEET Description Receive Loopback Interrupt Request Masks bit in this register and its corresponding interrupt request bit in register 25H are both set then the INT/IRQ lead goes active to signal an interrupt request to the external microprocessor. ...
Page 91
... Receive PMDL FIFO Interrupt Request Masks bit and its corre- sponding interrupt request bit in register 2CH are both set then the INT/IRQ lead goes active to signal an interrupt request to the external microprocessor M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
Page 92
... DEPTH 3B 7-0 RX FCS ERROR Counter TXC-03305-MB Ed. 4, September 2000 DATA SHEET Description Transmit PMDL FIFO Interrupt Request Masks bit and its corre- sponding interrupt request bit in register 2CH are both set then the INT/IRQ lead goes active to signal an interrupt request to the external microprocessor ...
Page 93
... PMDL FIFO transitions from more than half empty to half empty or has detected an end of message. When set to 0, the HDLC con- troller generates an interrupt only at the end of the message, or when a FIFO underflow has occurred M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
Page 94
... Reserved 1 RISE 0 FALL TXC-03305-MB Ed. 4, September 2000 DATA SHEET Description Enable HDLC Transmit Controller enables the Transmit PMDL con- troller. The PMDL C-bits in the transmit DS3 frame are derived from the transmit PMDL controller. The transmitter will send flags when the transmit PMDL FIFO is empty ...
Page 95
... TXC-02030 DS1 DS1 Figure 26. Example Channelized T3 Application Transwitch has a “Channelized T3 Reference Design” Technical Manual, document number TXC-21114-TM1, available for use with this device. It may be viewed or printed from the “Products/M13X” page of the Transwitch Wold Wide Web Site (www.transwitch.com). DATA SHEET ...
Page 96
... Values shown are for reference only. 2. Identification of the solder ball A1 corner is contained within this shaded zone. This package corner may be a 90° angle, or chamfered for A1 identification. 3. Size of array 16, JEDEC code MO-151/B-AAE-1 Figure 27. M13X TXC-03305 208-Lead Plastic Ball Grid Array Package TXC-03305-MB Ed. 4, September 2000 DATA SHEET ...
Page 97
... TRANSWITCH TXC-03305AIPQ LEAD #1 INDEX 208 1 25.50 SQ 28.00 0.10 SQ 30.60 0.25 SQ SEE DETAIL “A” Figure 28. M13X TXC-03305 208-Lead Plastic Quad Flat Package DATA SHEET 105 104 See Details “B” and “C” 0.09 4.07 (MAX) 0.20 Note: All dimensions shown are in millimeters and are nominal unless otherwise indicated ...
Page 98
... M13X TXC-03305 ORDERING INFORMATION Part Number: TXC-03305AIOG Part Number: TXC-03305AIPQ RELATED PRODUCTS TXC-02020, ART VLSI Device (Advanced STS-1/DS3 Receiver/Transmitter). ART performs the transmit and receive line interface functions required for transmission of STS-1 (51.840 Mbit/s) and DS3 (44.736 Mbit/s) signals across a coaxial interface. ...
Page 99
... TXC-05150, CDB VLSI Device (Cell Delineation Block). Provides cell delineation for ATM cells carried in a physical line at rates of 1.544 to 155 Mbit/s. TXC-06101, PHAST-1 VLSI Device (SONET STS-1 Overhead Terminator). This device provides features similar to those of the TXC-03011 SOT-1E device, but it operates from a power supply of 3.3 volts rather than 5 volts. DATA SHEET ...
Page 100
... Carondelet Avenue, Suite 407 Clayton, MO 63105-3329 ETSI (Europe): European Telecommunications Standards Institute 650 route des Lucioles 06921 Sophia Antipolis Cedex France TXC-03305-MB Ed. 4, September 2000 DATA SHEET Tel: (212) 642-4900 Fax: (212) 302-1286 Web: www.ansi.org Tel: (650) 949-6700 Fax: (650) 949-6705 Web: www ...
Page 101
... Tel: (800) 433-5177 (within U.S.A.) Tel: (503) 693-6232 (outside U.S.A.) Fax: (503) 693-8344 Web: www.pcisig.com Tel: (800) 521-CORE (within U.S.A.) Tel: (908) 699-5800 (outside U.S.A.) Fax: (908) 336-2559 Web: www.telcordia.com Tel: 3 3432 1551 Fax: 3 3432 1553 Web: www.ttc.or.jp - 101 - M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
Page 102
... Added last row to the Absolute Maximum Ratings and Environmental Limitations table that states the LATCH-UP specification. 95 Added reference to the Channelized T3 Reference Design in the Applications Section. 98 Changed reference to TXC-20153D in Related Products section to TXC-20153G. 100 -101 Changed Standards Documentation Sources section. 102 Changed List of Data Sheet Changes Section. ...
Page 103
... TranSwitch covering or relating to any combination, machine, or process in which such semicon- ductor products or services might be or are used. DATA SHEET - NOTE - - 103 - M13X TXC-03305 TXC-03305-MB Ed. 4, September 2000 ...
Page 104
... TranSwitch Corporation 3 Enterprise Drive • • Shelton, CT 06484 USA Tel: 203-929-8810 - 104 - • • Fax: 203-926-9453 www.transwitch.com ...
Page 105
... Communications Department at TranSwitch. Marketing Communications will ensure that the relevant Product Information Sheets, Data Sheets, Application Notes, Technical Bulletins and other publications are sent to you. You may also choose to provide the same information by fax (203.926.9453 e-mail (info@txc.com telephone (203.929.8810). Most of these documents will also be made immediately available for direct download as Adobe PDF files from the TranSwitch World Wide Web Site (www ...
Page 106
... Please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this TranSwitch product as it becomes available. • TranSwitch Corporation 3 Enterprise Drive (Fold back on this line second, then tape closed, stamp and mail.) TranSwitch Corporation Attention: Marketing Communications Dept. 3 Enterprise Drive Shelton, CT 06484-4694 U.S.A. • ...