TXC-03303-ARPQ Transwitch Corporation, TXC-03303-ARPQ Datasheet

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TXC-03303-ARPQ

Manufacturer Part Number
TXC-03303-ARPQ
Description
Manufacturer
Transwitch Corporation
Datasheet

Specifications of TXC-03303-ARPQ

Lead Free Status / RoHS Status
Compliant
Copyright
TranSwitch and TXC are registered trademarks of TranSwitch Corporation
FEATURES
• Multiplexes/demultiplexes 28 DS1 signals to/from
• M13 or C-bit parity mode operation
• FEBE, C, or P-bit parity error insertion capability
• DS3 idle signal generators
• DS1 idle signal (QRS, AIS or ESF) generators
• DS3 LOS, LOF, P-bit parity, C-bit parity, AIS and
• Receive or transmit DS1 LOS detectors
• DS2 LOF detectors
• External interface for receiving 14 C-bits and
• DS3 and DS2 X-bit access
• DS3 transmit and receive selectable AIS
• Supports Intel, Motorola, or multiplexed
• DS2 Tx/Rx X-bit control/status
• Test Access Port for boundary scan
• Single +5V, 5% power supply
• 208-pin plastic quad flat package
LINE SIDE
a DS3 signal.
idle detectors
transmitting either 13 or 14 C-bits based on a
control bit setting
generation and detection
microprocessor interfaces.
DS3 Receive
DS3 Transmit
Clock & Data
Clock & Data
1998 TranSwitch Corporation
TranSwitch Corporation
Tel: 203-929-8810
+5V
Microprocessor
Bus
3 Enterprise Drive
Extended Features
MUX/DEMUX,
Fax: 203-926-9453
Access
TXC-03303
Test
Port
DS3/DS1
M13E
Address
Leads
DESCRIPTION
Strap
APPLICATIONS
The M13E CMOS VLSI device provides the functions
needed to multiplex and demultiplex 28 independent DS1
signals to and from a DS3 signal with either an M13 or C-
bit frame format. It includes some extended features rel-
ative to the M13 device. The M13E line side signals typ-
ically interface with a TranSwitch ART or ARTE device,
DS3LIM-SN Module or other line circuitry; terminal side
signals interface with commercially available DS1 line
interface devices. A DS1 line interface device containing
an internal dejitter buffer is recommended.
The M13E provides an external transmit (13 or 14 bits) and
receive (14 bits) interface for the 21 C-bits while operating
in the C-bit parity mode. The FEAC channel (C3) can be
accessed via the external interface or the M13E memory.
The M13E memory map contains 35, 8-bit register loca-
tions for software control, performance counters, and
alarm reporting. The microprocessor interface provides
for connection to an Intel or Motorola-compatible micro-
processor, or for use of a multiplexed address/data bus.
• Single-board M13 multiplexer
• Compact add/drop mux
• Fractional T3
• DCS and EDSX
• CSU/DSU
DS3/DS1 MUX/DEMUX, Extended Features
Data, Clock,
Shelton, Connecticut 06484
C-Bits I/O
& Frame
www.transwitch.com
Channel 28 I/O
Clock & Data
Channel 1 I/O
Clock & Data
M13E Device
TERMINAL SIDE
DS1
DATA SHEET
DS1
Document Number:
Ed. 4, August 1998
USA
TXC-03303
TXC-03303-MB

Related parts for TXC-03303-ARPQ

TXC-03303-ARPQ Summary of contents

Page 1

... Clock & Data DS3 Transmit Clock & Data Microprocessor Copyright 1998 TranSwitch Corporation TranSwitch and TXC are registered trademarks of TranSwitch Corporation TranSwitch Corporation Tel: 203-929-8810 DS3/DS1 MUX/DEMUX, Extended Features DESCRIPTION The M13E CMOS VLSI device provides the functions needed to multiplex and demultiplex 28 independent DS1 signals to and from a DS3 signal with either an M13 or C- bit frame format ...

Page 2

... Marketing Department to receive relevant updated and supplemental documentation issued. They should also contact the Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product M13E TXC-03303 Page TXC-03303-MB Ed. 4, August 1998 ...

Page 3

... Figure 13. Microprocessor Write Cycle Timing - Intel Interface ....................... 27 Figure 14. Microprocessor Read Cycle Timing - Motorola Interface ................ 28 Figure 15. Microprocessor Write Cycle Timing - Motorola Interface ................ 29 Figure 16. Boundary Scan Timing ................................................................... 30 Figure 17. Boundary Scan Schematic ............................................................. 50 Figure 18. M13E TXC-03303 208-pin Plastic Quad Flat Package ................... M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 4

... This page has been intentionally left blank M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 5

... CCKT CFMT CDCCT Figure 1. M13E TXC-03303 Block Diagram BLOCK DIAGRAM DESCRIPTION Figure 1 shows a simplified block diagram of the M13E and its signal leads. In the receive direction, DS3 data (DS3DR) is clocked into the M13E on positive transitions of the DS3 input clock (DS3CR). The data and clock signals may be derived from any line interface device such as TranSwitch’ ...

Page 6

... C16, C17, C18, C19, C20, C21). The receive C-bit interface consists of a serial data output (CDR), an output clock (CCKR), a data link indicator pulse (CDCCR), and an output framing pulse (CFMR). The data link indica- tor pulse identifies the location of the three data link C-bits, C13, C14, and C15 M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 7

... C3 = Far End Alarm & Control (FEAC) C6* Not defined, set to one C9 C-Parity bits C12 Far End Block Error (FEBE) C15* Maintenance data link (28 kbit/s) C18* Not defined, set to one C21* Not defined, set to one Figure 2. C-Bit Assignments - 7 - M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 8

... DR25 CR25 CDCCT DR26 200 VDD CR26 DR27 CR27 DLEN 205 GND GND NC NC M13E TXC-03303 Pin Diagram (Top View) Figure 3. M13E TXC-03303 Pin Diagram - 8 - M13E TXC-03303 NC NC GND GND 100 DT27 CT27 DT26 CT26 DT25 95 CT25 VDD DS3DT CCKT CFMT ...

Page 9

... The DS1 clock signals are derived from the DS3 clock signal (DS3CR). During periods of DS3/DS2 out of frame or AIS, the M13E provides a DS1 clock signal for clock- ing out AIS which is derived from the XCK clock (pin 90 M13E TXC-03303 Name/Function TXC-03303-MB Ed. 4, August 1998 ...

Page 10

... Type Name/Function TTL Transmit DS1 Clocks Channels 1 - 28: Transmit data is clocked into the M13E on positive transitions. The clock for the first DS1 channel corresponds to CT1, while the clock for the last DS1 channel corresponds to CT28 M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 11

... DT25 96 DT26 98 DT27 100 DT28 109 Type Name/Function TTL Transmit DS1 Clocks (continued from previous page) TTL Transmit Data DS1 Channels 1 - 28: The first DS1 channel corresponds to DT1, while the last DS1 channel corresponds to DT28 M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 12

... Intel/Multiplexed - An active low signal generated by the microprocessor for reading the M13E register locations. Motorola - An active high signal generated by the micro- processor for reading the M13E register locations. An active low signal is used to write to the M13E register locations M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 13

... The Motorola compatible interface (680X0 family) con- sists of eight address leads, eight bidirectional data leads, select, read/write, and data transfer acknowledge M13E TXC-03303 Interface 1 Multiplexed 2 Multiplexed Intel Compatible Motorola Compatible TXC-03303-MB Ed. 4, August 1998 ...

Page 14

... C-bits from the C-bit data (CDR) into external circuitry. This signal is enabled by placing a high on the signal lead labeled DLEN M13E TXC-03303 Register Address 5 Register Address TXC-03303-MB Ed. 4, August 1998 ...

Page 15

... Data Link Enable: Normally left open. A high enables the transmit and receive data link indication signals, CDCCT and CDCCR. The data link indication signals identify the location of the three data link C-bits (C13, C14, and C15). TTLp TranSwitch Test Pin: Leave open M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 16

... M13E, this pin must be held low, to reset the TAP controller. Failure may cause the TAP controller to take control of the M13E output pins. When the bound- ary scan feature is not used, this pin must be held low M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 17

... TXC-03303 Unit Conditions V Note 1 + 0.5 V Note Note ft/min linear airflow Note 1 Level per EIA/JEDEC JESD22-A112-A % Note 2 % non-condensing V per MIL-STD-833D Method 3015.7 Unit Test Conditions o C/W 0 ft/min linear airflow Unit Test Conditions Inputs switching TXC-03303-MB Ed. 4, August 1998 M13E ...

Page 18

... Typ Max 2.0 0.8 0.5 1.4 5 M13E TXC-03303 Unit Test Conditions V 4.75 <V < 5. 4.75 <V < Unit Test Conditions V 4.75 <V < 5. 4.75 <V < Unit Test Conditions V 4.75 <V < 5. 4.75 <V < 5. 5.25; Input = TXC-03303-MB Ed. 4, August 1998 ...

Page 19

... Min Typ Max 2.0 0.8 10 5.5 - 0.5 0.4 8.0 -4.0 2.4 4.9 7.0 1.1 1.8 2 M13E TXC-03303 Unit Test Conditions 4.75 -1 4.75 2 LOAD LOAD Unit Test Conditions V 4.75 <V < 5. 4.75 <V < 4.75 -4 4.75 8 LOAD LOAD TXC-03303-MB Ed. 4, August 1998 ...

Page 20

... IH IL Figure 4. DS3 Receive Timing t CYC t PWH Symbol Min t 20.0 CYC -- 6.0 H Figure 5. DS3 Transmit Timing t CYC OD Symbol Min t 20.0 CYC -- M13E TXC-03303 + V )/2 for output OH OL Typ Max Unit 22. Typ Max Unit 22. 8.0 ns TXC-03303-MB Ed. 4, August 1998 ...

Page 21

... PWH PWL Symbol Min t 583 CYC t 174 PWH t 174 PWL -- M13E TXC-03303 Typ Max Unit 1300 ns 21 DS3CR ns Cycles 14 DS3CR ns Cycles 10 ns Typ Max Unit 648 712.8 ns 324 453 ns 324 453 and t are measured with respect SU H TXC-03303-MB Ed. 4, August 1998 ...

Page 22

... CFMR pulse width (high) Figure 8. C-Bit Receive Interface Timing CYC C13 C14 t D(1) Symbol Min t CYC t OD( OD(2) t D( TXC-03303 C15 C16 C17 C18 C19 C20 C21 t D(2) Typ Max 3800 3800 13 20 1900 3800 1900 TXC-03303-MB Ed. 4, August 1998 M13E Unit ...

Page 23

... CDCCT delay after CCKT CFMT pulse width Figure 9. C-Bit Transmit Interface Timing t CYC C5 C6 C13 C14 C15 t D(1) Symbol Min t CYC D( M13E TXC-03303 C16 C17 C18 C19 C20 C21 t D(2) Typ Max Unit 3800 3800 ns 1900 ns 3800 ns 1900 ns TXC-03303-MB Ed. 4, August 1998 ...

Page 24

... Note: The transmit clock (XCK) or receive clock (DS3CR) must be present for the microprocessor bus interface to operate H(1) t H(2) Addr t OD(3) t OD(2) t W(2) Symbol Min t 95 PW( W( H( OD(1) t OD(2) t OD(3) t 180 PW( W( TXC-03303 t W(1) t OD(1) Data t PW(2) Typ Max 20 50 150 80 TXC-03303-MB Ed. 4, August 1998 M13E Unit ...

Page 25

... WR wait after ALE Note: The transmit clock (XCK) or receive clock (DS3CR) must be present for the microprocessor bus interface to operate. t H(1) Data PW(2) t W(2) Symbol Min t 95 PW 200 PW( W( M13E TXC-03303 t W(1) t H(2) Typ Max Unit TXC-03303-MB Ed. 4, August 1998 ...

Page 26

... RD pulse width SEL set-up time to RD SEL hold time after RD Note: The transmit clock (XCK) or receive clock (DS3CR) must be present for the microprocessor bus interface to operate SU( Symbol Min SU( SU( H( M13E TXC-03303 t H( H(2) Typ Max Unit TXC-03303-MB Ed. 4, August 1998 ...

Page 27

... D(7-0) data hold time after WR SEL set-up time pulse width Note: The transmit clock (XCK) or receive clock (DS3CR) must be present for the microprocessor bus interface to operate. t SU(2) t SU( Symbol Min Typ SU( SU( H( SU( M13E TXC-03303 t H(1) t H(2) Max Unit TXC-03303-MB Ed. 4, August 1998 ...

Page 28

... Note: The transmit clock (XCK) or receive clock (DS3CR) must be present for the microprocessor bus interface to operate. t PW(1) t SU(2) t D(1) t PW(2) t D(2) Symbol Min SU(1) t D( PW( SU( H( PW( M13E TXC-03303 t H(1) t H( Typ Max Unit TXC-03303-MB Ed. 4, August 1998 ...

Page 29

... The DTACK signal lead is tri-stated when SEL is high. Note: The transmit clock (XCK) or receive clock (DS3CR) must be present for the microprocessor bus interface to operate SU(1) t PW(1) t SU(3) t PW( Symbol Min SU( SU( H( PW( SU( H( PW( TXC-03303 t H(1) t H(2) SU( Typ Max TXC-03303-MB Ed. 4, August 1998 M13E Unit ...

Page 30

... TDI hold time after TCK TDO delay from TCK TRS pulse width Figure 16. Boundary Scan Timing t PWH t H(1) t SU(1) t H(2) t SU( Symbol Min t 50 PWH t 50 PWL t 3.0 SU(1) t 2.0 H(1) t 3.0 SU(2) t 2.0 H( M13E TXC-03303 t PW Max Unit 7 TXC-03303-MB Ed. 4, August 1998 ...

Page 31

... TFEAC4 TFEAC3 TFEAC2 RFEAC3 RFEAC2 LLB21 LLB20 LLB11 1LBV3 1LBV2 1LBV1 R3AIS1 R3AIS0 T3AIS1 C1BZ3 C1BZ2 C1BZ1 ME3 ME2 ME1 TXC-03303-MB Ed. 4, August 1998 M13E Bit 0 XR1 XT DS2OOF1 FB0 CP0 PP0 D10 LB1 LB2 LB3 LB4 LOS1 LOS2 LOS3 LOS4 IDL1 ...

Page 32

... This permits the M13E microprocessor interface and multiplexer to function. Recovery occurs when the first clock transition is detected. Receive DS3 X-bit Number 2: This bit position indicates the receive state of X2. This bit position is updated each frame M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 33

... Transmit X-Bits: The X-bits may be used to transmit a yellow alarm or may be used as a low speed signaling channel. A one or zero causes the M13E to transmit a one or zero for both X1 and X2. Note: Set to 1 when transmit- ting DS3 idle signal (see T3IDL in this register 01H M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 34

... C1 Value Random All 1s In addition, any C-bit that is received as zero will index the C-bit Equals Zero Counter (C1BZCNT) in 22H TXC-03303 DS1 Idle Code Selected QRS) including zero Application M13 format C-bit parity format TXC-03303-MB Ed. 4, August 1998 M13E ...

Page 35

... Only the indication of one error count is held during the micropro- cessor read and the M13E write cycle. The counter is also inhibited during DS3 loss of signal or out of frame times. This counter is cleared when it is read by the microprocessor M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 36

... Channel DS3 For CON/DIS, Connect = 1, Disconnect = 0 For FEAC (C-bit parity mode only stuff bit inversion - 36 - M13E TXC-03303 D21 D20 D11 TXC-03303-MB Ed. 4, August 1998 0 D10 ...

Page 37

... DS1 channels indicated. For complete expla- nation, see 08H. Receive Loopback Requests: Bits 6-0 (LBn) indicate loopback requests sent by the distant end for the DS1 channels indicated. For complete expla- nation, see 08H M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 38

... DS1 channel in this location, the DS1 chan- nel is looped back instead. The loopback is from the Rx to the Tx direction. When the channel in this register is written with a 0, the DS1 transmit source is from the channel’s DTn/CTn pins M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 39

... The X-bits are the inverse of the two X-bits received. They latch when they are equal to zero. A microprocessor read cycle clears a set alarm alarm state or status condition remains true (a one), the corresponding bit relatches M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 40

... DS3 F-bits and M-bits in Error Counter: An 8-bit saturating counter that counts the number of DS3 F-bits and DS3 M-bits that are in error since the last read cycle. The counter is inhibited when DS3 loss of signal or out of frame occurs. The counter is cleared when it is read by the microprocessor M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 41

... Write Don’t Care) - M13E terminates FEAC word transmission - Transmission must be terminated before another FEAC word can be loaded and transmitted. Note: The C3CLKI bit in register 19H must be set this register is used to transmit a FEAC message M13E TXC-03303 1CH TXC-03303-MB Ed. 4, August 1998 ...

Page 42

... Line loopback activate and deactivate FEAC codes are not dis- played in this register. Also the individual line loopback activate and deactivate codewords are not displayed in this register M13E TXC-03303 1DH Status TXC-03303-MB Ed. 4, August 1998 ...

Page 43

... Channel Clear Channel Clear Channel Confirmed Initialization Register: This register location is used to reset and initialize the M13E. After power becomes stable Hex followed Hex must be written into this location M13E TXC-03303 --- D22 D21 D20 D11 D10 TXC-03303-MB Ed. 4, August 1998 ...

Page 44

... Undefined - Do not use 0 Third C-bit &/+* stuff bit inverted 1 Second C-bit &/+* stuff bit inverted 0 First C-bit &/+* stuff bit inverted 1 Stuff bit inverted 0 Stuff bit = 0 1 Stuff bit = 1 X Undefined - Do not use X Undefined - Do not use TXC-03303-MB Ed. 4, August 1998 M13E ...

Page 45

... TXC-03303 Framed 1010 pattern C-bits = 0 X-bits disregarded Framed 1010 pattern C-bits = 0 X-bits = 1 Framed 1010 pattern C-bits disregarded X-bits disregarded Framed 1111 pattern C-bits disregarded X-bits disregarded Unframed 1010 pattern Unframed all ones pattern Undefined - Do not use TXC-03303-MB Ed. 4, August 1998 M13E ...

Page 46

... DS3 M-bits in Error Counter: An 8-bit saturating counter that counts the number of M-bits that are in error since the last read cycle. The counter is inhibited when DS3 loss of signal or out of frame occurs. The counter is cleared when it is read by the microprocessor M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 47

... An SEF is defined as 3 out of 16 F-bits are in error, utilizing a sliding window of 16 bits. This is a latched bit, and clears when it is read by the microprocessor. This bit will relatch if the condition that causes this bit to latch is still present M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 48

... Resets internal counters and FIFOs. 00 Presets internal counters and FIFOs. ) pins which provide internal circuit isolation. All Delay (min.) Delay (typ.) Delay (max.) DRn 200 ns DS3DT 400 ns 4100 TXC-03303 Comments pins must be tied DD Notes 800 1-28 7800 1-28 TXC-03303-MB Ed. 4, August 1998 M13E ...

Page 49

... TDI input, through an internal scan cell, to the TDO pin. The purpose of this instruction is to abbreviate the scan path through the circuits that are not being tested to only a single clock delay M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 50

... Boundary Scan Register CORE LOGIC OF M13E DEVICE Instruction Register Test Data Registers TAP Controller TDI TDO TCK TMS TRS Control Pins IN OUT Boundary Scan Serial Test Data Figure 17. Boundary Scan Schematic - 50 - M13E TXC-03303 Signal input and output pins TXC-03303-MB Ed. 4, August 1998 ...

Page 51

... CR14 Output2 19 DR14 Output2 20 CR13 Output2 21 DR13 Output2 22 CR12 Output2 23 DR12 Output2 24 CR11 Output2 25 DR11 Output2 26 CR10 Output2 27 DR10 Output2 28 CR9 Output2 29 DR9 Output2 30 CR8 Output2 31 DR8 Output2 33 CR7 Output2 34 DR7 Output2 35 CR6 Output2 - 51 - M13E TXC-03303 Comments TXC-03303-MB Ed. 4, August 1998 ...

Page 52

... CR1 Output2 63 DR1 Output2 64 CFMR Output2 65 CCKR Output2 66 CDR Output2 68 DS3CR Input 69 DS3DR Input 71 RD Input 72 WR Input 73 ALE Input 74 SEL Input 76 A/D7 Input 76 A/D7 Output3 77 A/D6 Input 77 A/D6 Output3 - 52 - M13E TXC-03303 Comments TXC-03303-MB Ed. 4, August 1998 ...

Page 53

... DT26 Input 99 CT27 Input 100 DT27 Input 108 CT28 Input 109 DT28 Input 111 CT21 Input 112 DT21 Input 113 CT22 Input 114 DT22 Input 115 CT23 Input 116 DT23 Input 117 CT24 Input - 53 - M13E TXC-03303 Comments TXC-03303-MB Ed. 4, August 1998 ...

Page 54

... Input 144 TEST Input 125 DS3CT Output2 165 DT12 Input 167 CT5 Input 168 DT5 Input 169 CT6 Input 170 DT6 Input 171 CT7 Input 172 DT7 Input 173 CT8 Input 174 DT8 Input - 54 - M13E TXC-03303 Comments TXC-03303-MB Ed. 4, August 1998 ...

Page 55

... CR25 Output2 199 DR26 Output2 201 CR26 Output2 202 DR27 Output2 203 CR27 Output2 161 P1 Input 162 P0 Input 204 DLEN Input 164 OUTDIS Input 163 RDY/DTACK Output2 198 CDCCT Output2 150 TDO [SCAN Output M13E TXC-03303 Comments TXC-03303-MB Ed. 4, August 1998 ...

Page 56

... The M13E device is packaged in a 208-pin plastic quad flat package suitable for surface mounting, as illus- trated in Figure 18. 156 157 PIN #1 INDEX 208 1 SEE DETAIL “A” 0 Figure 18. M13E TXC-03303 208-Pin Plastic Quad Flat Package TRANSWITCH TXC-03303-AIPQ 25.50 SQ 28.00 0.10 SQ 30.60 0.25 SQ +0.08 0.15 -0 ...

Page 57

... Mbit/s) or STS-1 (51.840 Mbit/s) signals across a coaxial interface. The ARTE is an extended-feature version of the ART larger package. TXC-03103, QT1F- Plus VLSI Device (Quad T1 Framer- Plus ). The QT1F- Plus is a 4-channel DS1 framer designed for voice and data communications applications. AMI, B8ZS, and NRZ line codes are supported ...

Page 58

... Publication Services of International Telecommunication Union (ITU) Telecommunication Standardization Sector (T) Place des Nations CH 1211 Geneve 20, Switzerland Tel: 41-22-730-5285 Fax: 41-22-730-5991 ATM Forum European Office 14 Place Marie - Jeanne Bassot Levallois Perret Cedex 92593 Paris France Tel Fax M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 59

... Standardization Documents Order Desk 700 Robbins Avenue Building 4D Philadelphia, PA 19111-5094 Tel: 212-697-1187 Fax: 215-697-2978 TTC (Japan): TTC Standard Publishing Group of the Telecommunications Technology Committee 2nd Floor, Hamamatsucho - Suzuki Building, 1 2-11, Hamamatsu-cho, Minato-ku, Tokyo Tel: 81-3-3432-1551 Fax: 81-3-3432-1553 - 59 - M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 60

... Changed first and last paragraphs of Description for Receive Loopback Requests in register 08H. Added last sentence to Description for Receive Loopback Requests in register 09H. Edition 4, August 1998 Edition 3, June 1996 Summary of the Change and t in both tables. Changed PWH PWL and t . D(1) H( M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 61

... Added Boundary Scan Reset section. 51-55 Made major changes to Scan Cell table and added note at the bottom of page 51. 57 Updated Related Products list. 58-59 Updated Standard Documentation Sources list. 60 Replaced List of Data Sheet Changes. Summary of the Change - 61 - M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 62

... NOTES - - 62 - M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 63

... Nor does TranSwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TranSwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. - NOTES - - 63 - M13E TXC-03303 TXC-03303-MB Ed. 4, August 1998 ...

Page 64

... TranSwitch Corporation 3 Enterprise Drive Engines for Global Connectivity • • Shelton, CT 06484 USA Tel: 203-929-8810 - 64 - • • Fax: 203-926-9453 www.transwitch.com ...

Page 65

... Please fax this page to Mary Lombardo at (203) 926-9453 or fold, tape and mail it (see other side) ___________ Country: ______________ Windows Sun __________ __________ __________ - 65 - TXC-03303 Mac UNIX Solaris HP Other __________ TXC-03303-MB Ed. 4, August 1998 M13E ...

Page 66

... TranSwitch product as it becomes available. • TranSwitch Corporation 3 Enterprise Drive Engines for Global Connectivity (Fold back on this line second, then tape closed, stamp and mail.) TranSwitch Corporation Attention: Mary Lombardo 3 Enterprise Drive Shelton, CT 06484 U.S.A. • • ...

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