TTSV04622V2-DB LSI, TTSV04622V2-DB Datasheet
TTSV04622V2-DB
Specifications of TTSV04622V2-DB
Related parts for TTSV04622V2-DB
TTSV04622V2-DB Summary of contents
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TDCS4810G SONET/SDH 10 Gbits/s APS Port and TSI Features 10 Gbit bidirectional data path with common frame I synchronization and clocking. Versatile IC which supports an aggregate band- I width of 30 Gbits/s. Supports flexible 48-channel STS-12 data links. I ...
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Gbits/s APS Port and TSI Contents Features .................................................................................................................................................................... 1 Interface .................................................................................................................................................................. 1 Cross Connect ........................................................................................................................................................ 1 Protection Switching ............................................................................................................................................... 1 Microprocessor Interface ........................................................................................................................................... 1 Applications ............................................................................................................................................................... 6 Description.................................................................................................................................................................6 Receive Interface ....................................................................................................................................................7 Fabric Core ............................................................................................................................................................. 7 Transmit Interface ................................................................................................................................................... 7 ...
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... Figure 3. Suggested Schematic for 1.0 V and 1.4 V Reference Voltages .............................................................. 25 Figure 4. Transmitter TOH on LVDS Output .......................................................................................................... 38 Figure 5. SYS_FP Timing Requirements ............................................................................................................... 38 Figure 6. Receiver Block Diagram.......................................................................................................................... 42 Figure 7. Framer State Machine............................................................................................................................. 43 Figure 8. TSHIM Timeline....................................................................................................................................... 45 Figure 9. Connection Memory Physical Organization ............................................................................................ 46 Figure 10. Connection Memory Entry..................................................................................................................... 47 Figure 11. APS Byte Handling................................................................................................................................ 48 Figure 12 ...
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Gbits/s APS Port and TSI Contents Table 1. Pin Assignments for 792-Pin LBGA by Pin Number Order......................................................................... 9 Table 2. Pin Assignments for 792-Pin LBGA by Signal Name Order ..................................................................... 14 Table 3. Pin Descriptions—Receive Interface ........................................................................................................ 19 Table ...
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May 2001 Contents Table 52. Audit Memory [23:0] (RO)....................................................................................................................... 65 Table 53. S1 Generation Status (RO) .................................................................................................................... 65 Table 54. S1 Generation Force Toggle (R/W)........................................................................................................ 65 Table 55. Channel Alarm Register (W1C) .............................................................................................................. 66 Table 56. Channel Alarm Mask Register ...
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... SONET/SDH test equipment. I TDCS4810G will interface seamlessly to a number of Agere Systems Inc. existing/next-generation high-speed I framers. Description The TDCS4810G has four sections: receive interface channels, a cross connect fabric core, transmit channels, and a microprocessor interface. The block diagram of the TDCS4810G is shown in Figure 1. All data stream channels must be synchronous in frequency, but can be asynchronous in phase. ...
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... The receiver performs three major functions, which are described in greater detail in upcoming sections: the clock and data recovery (CDR), the framer, and the FIFO aligner. Fabric Core The cross connect has 48 input channels and 48 out- put channels ...
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Gbits/s APS Port and TSI Pin Information Figure 2. Pin Diagram of 792 LBGA (Bottom View ...
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May 2001 Pin Information (continued) Table 1. Pin Assignments for 792-Pin LBGA by Pin Number Order Pin Signal Name Pin D_OUT0_11 B3 A4 D_OUT0_08 B4 A5 REF14_0 B5 A6 D_OUT0_05 B6 ...
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Gbits/s APS Port and TSI Pin Information (continued) Table 1. Pin Assignments for 792-Pin LBGA by Pin Number Order (continued) Pin Signal Name Pin D_OUT0_13_N F3 E4 D_OUT0_13 ...
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May 2001 Pin Information (continued) Table 1. Pin Assignments for 792-Pin LBGA by Pin Number Order (continued) Pin Signal Name Pin N34 UNUSED T37 N35 UNUSED T38 N36 V T39 DD2 N37 N38 UNUSED U2 N39 NC ...
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Gbits/s APS Port and TSI Pin Information (continued) Table 1. Pin Assignments for 792-Pin LBGA by Pin Number Order (continued) Pin Signal Name Pin AF34 UNUSED AJ37 V AF35 UNUSED AJ38 NC AF36 UNUSED AJ39 NC AF37 UNUSED AK1 ...
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May 2001 Pin Information (continued) Table 1. Pin Assignments for 792-Pin LBGA by Pin Number Order (continued) Pin Signal Name Pin AR28 V AT31 V DDA AR29 D_OUT2_01 AT32 UNUSED AR30 D_OUT2_03 AT33 V AR31 RESLO_2 AT34 D_OUT2_07_N AR32 D_OUT2_06 ...
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Gbits/s APS Port and TSI Pin Information (continued) Table 2. Pin Assignments for 792-Pin LBGA by Signal Name Order Signal Name Pin Signal Name ADDRESS_0 V35 D_IN0_04 ADDRESS_1 V34 D_IN0_04_N ADDRESS_2 U39 D_IN0_05 ADDRESS_3 U38 D_IN0_05_N ADDRESS_4 U35 D_IN0_06 ...
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May 2001 Pin Information (continued) Table 2. Pin Assignments for 792-Pin LBGA by Signal Name Order (continued) Signal Name Pin Signal Name NC AV18 D_OUT1_02 NC AT19 D_OUT1_02_N B32 NC AR19 D_OUT1_03 D_OUT0_00 A9 D_OUT1_03_N F30 D_OUT0_00_N B9 D_OUT1_04 D_OUT0_01 ...
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Gbits/s APS Port and TSI Pin Information (continued) Table 2. Pin Assignments for 792-Pin LBGA by Signal Name Order (continued) Signal Name Pin Signal Name NC E38 NC NC E39 ...
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May 2001 Pin Information (continued) Table 2. Pin Assignments for 792-Pin LBGA by Signal Name Order (continued) Signal Name Pin Signal Name NC AP4 SYS_FP_N NC AP36 TA_N NC AP37 TCK NC AP38 TDI NC AP39 TDO NC AR1 TEA_N ...
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Gbits/s APS Port and TSI Pin Information (continued) Table 2. Pin Assignments for 792-Pin LBGA by Signal Name Order (continued) Signal Name Pin Signal Name V AE3 V DD DD2 V AE37 V DD DD2 V AJ3 V DD ...
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May 2001 Pin Information (continued) Table 3. Pin Descriptions—Receive Interface Note: The speed for each channel below is 622.08 Mbits/s. Pin Symbol Type A10 D_IN0_00 I B10 D_IN0_00_N LVDS A11 D_IN0_01 I B11 D_IN0_01_N LVDS E13 D_IN0_02 I F13 D_IN0_02_N ...
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Gbits/s APS Port and TSI Pin Information (continued) Table 3. Pin Descriptions—Receive Interface (continued) Note: The speed for each channel below is 622.08 Mbits/s. * Pin Symbol Type A30 D_IN1_00 I B30 D_IN1_00_N LVDS A29 D_IN1_01 I B29 D_IN1_01_N ...
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May 2001 Pin Information (continued) Table 3. Pin Descriptions—Receive Interface (continued) Note: The speed for each channel below is 622.08 Mbits/s. * Pin Symbol Type AW30 D_IN2_00 I AV30 D_IN2_00_N LVDS AW29 D_IN2_01 I AV29 D_IN2_01_N LVDS AR27 D_IN2_02 I ...
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Gbits/s APS Port and TSI Pin Information (continued) Table 4. Pin Descriptions—Transmit Interface Note: The speed for each channel below is 622.08 Mbits/s. * Pin Symbol Type A9 D_OUT0_00 O B9 D_OUT0_00_N LVDS E11 D_OUT0_01 O F11 D_OUT0_01_N LVDS ...
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May 2001 Pin Information (continued) Table 4. Pin Descriptions—Transmit Interface (continued) Note: The speed for each channel below is 622.08 Mbits/s. * Pin Symbol Type A31 D_OUT1_00 O B31 D_OUT1_00_N LVDS E29 D_OUT1_01 O F29 D_OUT1_01_N LVDS A32 D_OUT1_02 O ...
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Gbits/s APS Port and TSI Pin Information (continued) Table 4. Pin Descriptions—Transmit Interface (continued) Note: The speed for each channel below is 622.08 Mbits/s. * Pin Symbol Type AW31 D_OUT2_00 O AV31 D_OUT2_00_N LVDS AR29 D_OUT2_01 O AP29 D_OUT2_01_N ...
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May 2001 Pin Information (continued) Table 5. Pin Descriptions—LVDS Reference Cell Pins * Pin Symbol Type B5 REF10_0 I E31 REF10_1 I AV35 REF10_2 I AR9 REF10_3 I A5 REF14_0 I F31 REF14_1 I AW35 REF14_2 I AP9 REF14_3 I ...
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Gbits/s APS Port and TSI Pin Information (continued) Table 6. Pin Descriptions—Microprocessor Interface * Pin Symbol Type V36 MPMODE_1 I V37 MPMODE_0 W39 PCLK I V38 CS_N I V39 TS_N I W35 DS_N I W36 RW_N I AF39 TA_N ...
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May 2001 Pin Information (continued) Table 6. Pin Descriptions—Microprocessor Interface (continued) * Pin Symbol Type AE38 DATA_15 I/O AE39 DATA_14 I/O AD36 DATA_13 I/O AD37 DATA_12 I/O AD38 DATA_11 I/O AD39 DATA_10 I/O AC34 DATA_9 I/O AC35 DATA_8 I/O AC38 ...
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Gbits/s APS Port and TSI Pin Information (continued) Table 8. Pin Descriptions—PLL References Pin Symbol Type D12 REXT0 — D28 REXT1 — AT28 REXT2 — Table 9. Pin Descriptions—JTAG Interface * Pin Symbol Type u W1 TCK I u ...
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May 2001 Pin Information (continued) Table 10. Pin Descriptions—Power and Ground Pin Symbol D9, D13, D17, V DD2 D23, D27, D31, E5, E6, E20, E34, E35, F5, F6, F19, F20, F21, F34, F35, J4, J36, N4, N36, U4, U36, W6, ...
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Gbits/s APS Port and TSI Pin Information (continued) Table 10. Pin Descriptions—Power and Ground (continued) Pin Symbol C3, C4, C9, C13 C17, C19, C20, C21, C23, C27, C31, C36, C37, D3, D4, D7, D11, D15, D20, D25, ...
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May 2001 Pin Information (continued) Table 11. Pin Descriptions—No Connect Pin Symbol E1, E2, E38, E39, NC F1, F2, F3, F4, F36, F37, F38, F39, G1, G2, G38, G39, H3, H4, H5, H6, H34, H35, H36, H37, H38, H39, J1, ...
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Gbits/s APS Port and TSI Pin Information (continued) Table 11. Pin Descriptions—No Connect (continued) Pin Symbol AM34, AM35, NC AM36, AM37, AN1, AN2, AN38, AN39, AP1, AP2, AP3, AP4, AP7, AP8, AP9, AP10, AP11, AP13, AP14, AP15, AP16, AP17, ...
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May 2001 Pin Information (continued) Table 12. Pin Descriptions—Unused Pins Pin Symbol A19, A21, UNUSED C8, C10, C30, C32, D8, D10, D14, D16, D18, D22, D24, D26, D30, D32, H1, H2, M1, M2, M38, M39, N1, N2, N5, N6, N34, ...
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Gbits/s APS Port and TSI Pin Information (continued) Table 13. Pin Summary Pin Type Pin Direction LVDS Reference Cell Pins CMOS Bidirectional NC UNUSED Other (Center taps, external resistors, diodes) Power Ground Total 34 Count Input 100 Output 96 ...
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May 2001 Overview Byte Ordering Each channel carries an STS-12 worth of data. The ordering of bytes within the STS-12 is shown in Table 14. In the case of an STS-192, each of the STS-12 channels comprising the STS-192 carries ...
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... MHz clock. Note that parallel data is not byte-aligned at this point. The framer is responsible for locking onto the STS-12 frame. It does so by first finding the byte boundary within the received 8-bit data bus and then identifying A1/A2 transitions ...
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May 2001 Overview (continued) Cross Connect (continued) next A1/A2 boundary; the switch is made during the S1 byte time. The trigger for a switch is configurable on a per-channel basis. The possible triggers are the follow- ing: The SYNC_N pin. ...
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Gbits/s APS Port and TSI Overview (continued) Transmit Interface The transmitter is composed of 48 STS-12 channels that are always treated as independent channels. Each of the outgoing LVDS serial streams of the transmitter transmits at a rate of ...
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May 2001 Overview (continued) Frame Pulse (continued) If SYS_CLK rises in under 2 ns after the rising edge of the frame pulse, the SYS_CLK will not sample the frame pulse until its next rising edge. The frame pulse detection is ...
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... Framer status (LOF) and A1/A2 frame error count are reported. These features are provisionable on a per-channel basis: — Framer status is implemented as a simple LOF latched alarm. While the framer state machine is in the LOF state, this bit is forced active meant to report any LOF occurrence as well as to ...
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May 2001 Overview (continued) Test Features (continued) Scrambler/Descrambler Disable: A scrambler/descrambler disable feature is provided, allowing the user to dis- I able the scrambler of the transmitter and the descrambler of the receiver. Note that B1 should then be calculated ...
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Gbits/s APS Port and TSI Functional Description Receiver Block The receiver block converts the incoming LVDS serial stream into an 8-bit parallel bus. The output bus is synchro- nized to the system clock and the frame is synchronized to ...
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... If an LVDS input is unconnected (floating), the LVDS clock recovery continues to provide a valid clock for downstream logic: internal logic timing is not violated and logic does not lock up. In such a case, loss of fram- ing occurs. The framer also goes back to the in-frame CONFIRM PATTERN A1/A2 CONFIRMED Notes: Row, column, and STS counters are only set/reset by state transition from LOF to frame confirm ...
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... LOF state even if there is a clear command from the CPU interface). The LOF counter is incremented each time the framer state machine goes into the LOF state. The A1/A2 error counter is incremented (one count per errored STS12 frame) upon detection of an error on either A1 byte of STS-1# byte of STS-1#1 ...
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May 2001 Functional Description (continued) Receiver Block (continued) TIME EXAMPLE: THREE NONALIGNED STREAMS. D_IN0_00 FIRST BIT OF FIRST A1 BYTE D_IN0_01 D_IN0_02 D_OUT0_00 D_OUT0_01 D_OUT0_02 Note: A clock is defined as 12.86 ns. Agere Systems Inc. INPUT WINDOW 63 CLOCKS ...
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Gbits/s APS Port and TSI Functional Description (continued) Receiver Block (continued) AIS Insertion Receiver behavior under the LOF event is under software control possible to select either insert AIS or pass- through when an LOF condition occurs ...
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May 2001 Functional Description (continued) Cross Connect Block (continued) Since only one of the two memories is in use for switching at any time, read operations can be carried out on the other memory. Thus, the preferred method of setting ...
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Gbits/s APS Port and TSI Functional Description (continued) Cross Connect Block (continued) APS Byte Handling As described in the general description section, incoming K1 and K2 are stored and monitored for a change and the outgoing K1 and K2 ...
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May 2001 Functional Description (continued) Cross Connect Block (continued) E1/F1/E2 Extraction The E1, F1, and E2 bytes carry information that can be used to initiate a switch. The E1 and F1 bytes contain path status information, and the E2 byte ...
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Gbits/s APS Port and TSI Functional Description (continued) Cross Connect Block (continued) The E1/F1 bytes for each STS-1 are used, but the E2 byte of only the STS each channel (STS-12) is used. The E2 byte for ...
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May 2001 Functional Description (continued) Transmitter Block The transmitter is composed of 48 STS-12 channels that are treated as independent channels. DATA FROM CROSS CONNECT A1/A2 A1/A2 ERROR INSERT VALUE (SOFTWARE REGISTER) Agere Systems Inc. B1 ERROR MASK INSERT COMMAND ...
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Gbits/s APS Port and TSI Functional Description (continued) Transmitter Block (continued) STS-12 Input Format Each of the 48 parallel input buses from the cross connect is synchronized to the system clock. The data stream format is a standard SONET ...
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May 2001 Functional Description (continued) Back-to-Back Cross Connect When data is fed into the TDCS4810G, it must not loop back into the TDCS4810G through another TDCS4810G without another device, with pointer mover or pointer processor capability, between them to align ...
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Gbits/s APS Port and TSI Register Descriptions The address shown for each register is the address of the first occurrence of the register. The number following the T character is the offset to the register for the next time ...
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May 2001 Register Descriptions (continued) Table 18. Memory Map Summary (continued) Address 0x0400— Port 1: See per-port structure above. 0x05FF 0x0600— Port 2: See per-port structure above. 0x07FF 0x0800— RESERVED. 0x09FF 0x0A00— RESERVED. 0x0AFF 0x0B00 Audit memory port 0. 0x0B17 ...
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... Although all alarms will be cleared on reset, some alarms may be asserted shortly after reset. For example, the LOF alarm is cleared on reset and then immediately asserted by the framer (which resets to the LOF state). Other alarms are also affected, but exactly which alarms are asserted after reset depends on the application. ...
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May 2001 Register Descriptions (continued) Device-Level Registers These registers appear only once in the device. Table 19. Device Interrupt Status Register (RO) Address Bit Name (Hex) 0000 14 ALM_SW 13 ALM_CH 12 ALM_DEV ALM_LS2 7 ALM_PS2 ...
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Gbits/s APS Port and TSI Register Descriptions (continued) Device-Level Registers (continued) Table 20. Device Interrupt Status Mask Register (R/W) Address Bit Name (Hex) 0001 14 ALM_SW_MSK 13 ALM_CH_MSK 12 ALM_DEV_MSK ALM_LS2_MSK 7 ALM_PS2_MSK 6 ALM_APS2_MSK ...
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May 2001 Register Descriptions (continued) Device-Level Registers (continued) Table 22. Channel Alarm Interrupt Status Mask Register (R/W) Address Bit Name (Hex) 0003 6 ALM_CH2_MSK 5 ALM_CH1_MSK 4 ALM_CH0_MSK 3 2 ALM_SW2_MSK 1 ALM_SW1_MSK 0 ALM_SW0_MSK - Table 23. Device Level ...
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Gbits/s APS Port and TSI Register Descriptions (continued) Device-Level Registers (continued) Table 26. Device Vintage Register (RO) Address Bit Name (Hex) 0007 15—0 CHIP_VINTAGE Table 27. Scratch Pad Register (R/W) Address Bit Name (Hex) 0008 15—0 SCRATCH_PAD Table 28. ...
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May 2001 Register Descriptions (continued) Device-Level Registers (continued) Table 29. Device Control Register (R/W) Address Bit Name (Hex) 000A 6 SW_SYNC 5 ALMFRZ 4 CNTFRZ 3—0 A1A2INSCNT Table 30. Frame Offset Register (R/W) Address Bit Name (Hex) 000B 13—0 FRMOFFS ...
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Gbits/s APS Port and TSI Register Descriptions (continued) Port (STS-192) Level Registers These registers appear once for each group of 16 channels. Thus, they are replicated three times in the device. Table 34. Channel Alarm Interrupt Status (Consolidation) Register ...
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May 2001 Register Descriptions (continued) Port (STS-192) Level Registers Table 39. Line Status (E2) Change Mask (R/W) Address Bit Name (Hex) 0205 15—0 E2ALM_MSK P+200 Table 40. APS (K1K2) Change Alarm (W1C) Address Bit Name (Hex) 0206 15—0 K1K2ALM P+200 ...
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Gbits/s APS Port and TSI Register Descriptions (continued) Port (STS-192) Level Registers Table 44. FIFO Thresholds (R/W) Address Bit Name (Hex) 0280 11—6 FIFOMAX P+200 5—0 FIFOMIN Note: Thresholds are compared to (N – 1) where N is the ...
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May 2001 Register Descriptions (continued) Port (STS-192) Level Registers Table 50. Audit Memory Control (R/W) Address Bit Name (Hex) 0286 4 AUDSTART* P+200 3—0 AUDCH * When this bit changes from the active configuration of the channel ...
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Gbits/s APS Port and TSI Register Descriptions (continued) Channel-Level Registers These registers appear once for each channel. Thus, they are replicated 48 times in the device. Table 55. Channel Alarm Register (W1C) Address Bit Name (Hex) 020A 3 FIFOERR ...
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May 2001 Register Descriptions (continued) Channel-Level Registers (continued) Table 58. Path Status (E1/F1) Change Alarm Mask (R/W) Address Bit Name (Hex) 022B 11—0 E1F1ALM_MSK P+200 C+2 Table 59. Channel Provisioning Register (R/W) Address Bit Name (Hex) 0300 9—8 SYNC_SRC P+200 ...
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Gbits/s APS Port and TSI Register Descriptions (continued) Channel-Level Registers (continued) Table 60. Channel Control Register (R/W) Address Bit Name (Hex) 0301 12 READE1F1 P+200 11 FAISL C+ FRMERRINS 8 B1COREN 7—0 B1CRPT Table 61. APS Control ...
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May 2001 Register Descriptions (continued) Channel-Level Registers (continued) Table 64. Channel Path Switch Control (R/W) Address Bit Name (Hex) 0307 11—0 WP[11:0] P+200 C+10 Table 65. Channel Path Switch Readback (RO) Address Bit Name (Hex) 0308 11—0 WPRDBK[15:0] P+200 C+10 ...
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Gbits/s APS Port and TSI Register Descriptions (continued) Channel-Level Registers (continued) Table 70. Channel Alarm Freeze Register (RO) Address Bit Name (Hex) 030D 4 P+200 3 FIFOERR_FZ C+10 2 B1ERR_FZ 1 LOF_FZ 0 FRMOFFS_FZ Note:The errors that occur between ...
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May 2001 Register Descriptions (continued) STS-1 Level Registers (continued) Table 72. Connection Memory AD (R/W) Address Bit Name (Hex) 100C 9—6 SRCTS C+40 5—0 SRCCH T+1 Table 73. Connection Memory BC (R/W) Address Bit Name (Hex) 1020 9—6 SRCTS C+40 ...
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Gbits/s APS Port and TSI Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at ...
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May 2001 Electrical Characteristics Power Sequencing The device power may be applied concurrently to both voltage level inputs. If power sequencing is used for other devices on a board system preferred that the highest ...
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Gbits/s APS Port and TSI Electrical Characteristics LVDS DRIVER 100 Ω Figure 17. LVDS Driver and Receiver and Associated Internal Components DRIVER (continued) CENTER TAP EXTERNAL DEVICE PINS INTERCONNECT ...
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May 2001 Electrical Characteristics LVDS Receiver Buffer Capabilities A disabled or unpowered LVDS receiver can withstand a driving LVDS transmitter over the full range of driver oper- ating range, for an unlimited period of time, without being damaged. Table 79 ...
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Gbits/s APS Port and TSI Electrical Characteristics Table 81. LVDS Driver Reference Data Parameter REF10E, REF10L Voltage Range REF14E, REF14L Voltage Range Nominal Input Current—REF10 and REF14 Reference Inputs Table 82. LVDS Receiver Data Parameter Receiver input Voltage Range, ...
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May 2001 Timing Characteristics Microprocessor Interface Timing The I/O timing specifications for the microprocessor interface are given in Table 84. The read and write timing dia- grams for all three microprocessor interface modes are shown in Figures 20—24. Table 84. ...
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Gbits/s APS Port and TSI Timing Characteristics (continued) Microprocessor Interface Timing Synchronous Mode—M860 The synchronous microprocessor interface (like Motorola MPC860) mode is selected when MPMODE = 10 or 11. Parity is selected when MPMODE = 10; no parity is ...
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May 2001 Timing Characteristics (continued) Microprocessor Interface Timing PCLK CS_N TS_N RW_N ADDRESS_[12:0] DATA_[15:0]/ PARITY_[1:0] (OUTPUT) HIGH Z TA_N/TEA_N Figure 21. M860 Synchronous Read Cycle (MPMODE = 10 or 11) Table 86. TA_N/TEA_N Cycle Termination for Synchronous Read Cycle TA_N ...
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Gbits/s APS Port and TSI Timing Characteristics (continued) Microprocessor Interface Timing Asynchronous Mode—M360 The asynchronous microprocessor interface (like Motorola MC68360) mode is selected when MPMODE = 00. Interface timing for the asynchronous mode write cycle is given in Figure ...
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May 2001 Timing Characteristics (continued) Microprocessor Interface Timing ADDRESS_[12:0] t10 CS_N t10 TS_N t10 DS_N RW_N HIGH Z TA_N/TEA_N DATA_[15:0] Figure 23. M360 Asynchronous Read Cycle (MPMODE = 00) Table 88. TA_N/TEA_N Cycle Termination for Asynchronous Read Cycle TA_N TEA_N ...
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Gbits/s APS Port and TSI Timing Characteristics (continued) Microprocessor Interface Timing DSP Synchronous Mode The synchronous digital signal processor interface (like Motorola DSP56309) mode is selected when MPMODE = 01. The DSP mode allows for five-cycle read/write only when ...
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May 2001 Outline Diagram 792-Pin LBGA Dimensions are in millimeters BALL CORNER 1.96/2.27 1.33/1. 1.00 Note: A dimension x/y refers to the minimum and maximum values for the given parameter. Agere Systems Inc. 40.00 ± 0.10 ...
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Gbits/s APS Port and TSI Outline Diagram (continued) 792-Pin LBGA (continued) Table 89. Basic 792-Pin LBGA Act. Ball Pitch Width/Length Balls mm (mils) 792 1.00 (39.4) * Maximum height from the board to the top surface of the package ...
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May 2001 Revision History May 2001—Rev 2 Pin Information Page 25, Table 5, added second footnote (†) and I reworked name/description for rows F9—AR31. Page 25, Figure 3, added to document. I Register Descriptions Page 66, Table 55 and Table ...
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... Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Copyright © ...