PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 24

• Manufacturer Part Number: PEF2256EV22NP
• Manufacturer: Lantiq

Specifications of PEF2256EV22NP

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.7
Changes in the PCM mode bit (FMR1.PMOD) or write operations to the GCM5 or GCM6
Register may result in an enlarged pulse width on the transmit line interface.
Note: A PLL reset will result in a brief disturbance of the traffic on the port and may cause
Therefore a power down of the analog transmitter for a period of 10 µs must be done for
proper operation. That can be performed in three different ways:
One of the three methods is sufficient to perform a power down of the analog transmitter.
Afterwards the corresponding bit has to be re configured to the desired value. It should
be taken care that the main PLL of the device is locked during leaving the power down
state. The locked state of the main PLL is indicated by GIS.PLLL = 1.
Note:
1. Take care that the main PLL of the device is locked during leaving the power down
2. It is suggested to configure the Registers GCM5, GCM6 and FMR1 before
2.8
An idle code configured in the register IDLE and configured to be sent out in certain
timeslots configured in ICB(3:1) registers is not transmitted in case the timeslot is also
configures as a "cleared" channel (configured by CCB(3:1) registers). Instead of the
IDLE code a ´FF
Data Sheet
– LIM1.DRS = 1,
– FMR0.XC(1:0) = 00 or
– GCR.PD = 1
state. The locked state of the main PLL is indicated by bit GIS.PLLL = 1.
configuring the register FMR0 during the initial device configuration.
a pulse width mismatch.
Transmit Pulse Width
Idle Pattern Insertion in Clear T1 Channels
H
‘ is transmitted in the corresponding timeslot.
24
Functional Restrictions
Rev. 1.1, 2005-06-13
PEF 2256 H/E
FALC
®
56