PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 59

• Manufacturer Part Number: PEF2256EV22NP
• Manufacturer: Lantiq

Specifications of PEF2256EV22NP

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.3
5.3.1
The communication between the CPU and the FALC
accessible registers. The interface can be configured as Intel or Motorola type with a
selectable data bus width of 8 or 16 bits.
The CPU transfers HDLC data to and from the FALC
per direction), sets the operating modes, controls function sequences, and gets status
information by writing or reading control and status registers. All accesses can be done
as byte or word accesses if enabled. If 16-bit bus width is selected, access to
lower/upper part of the data bus is determined by address line A0 and signal BHE/BLE
as shown in
Table 10
structure and interface type. The switching of ALE allows the FALC
connected to a multiplexed address/data bus.
5.3.1.1
Reading from or writing to the internal FIFOs (RFIFO and XFIFO) can be done using a
8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode.
Randomly mixed byte/word access to the FIFOs is allowed without any restrictions.
Table 8
BHE
0
0
1
1
Table 9
BLE
0
0
1
1
Data Sheet
A0
0
1
0
1
A0
0
1
0
1
shows how the ALE (Address Latch Enable) line is used to control the bus
Functional Blocks
Microprocessor Interface
Mixed Byte/Word Access to the FIFOs
Table 8
Data Bus Access (16-Bit Intel Mode)
Data Bus Access (16-Bit Motorola Mode)
Register Access
FIFO word access
Register word access (even addresses)
Register byte access (odd addresses)
Register byte access (even addresses)
No transfer performed
Register Access
FIFO word access
Register word access (even addresses)
Register byte access (odd addresses)
Register byte access (even addresses)
No transfer performed
and
Table
9.
59
Functional Description E1/T1/J1
®
®
56 is done using a set of directly
56 (through 64-byte deep FIFOs
FALC
D(15:0)
D(15:8)
D(7:0)
None
FALC
D(15:0)
D(7:0)
D(15:8)
None
®
®
56 Data Pins Used
56 Data Pins Used
Rev. 1.1, 2005-06-13
®
56 to be directly
PEF 2256 H/E
FALC
®
56