82P2282PF IDT, Integrated Device Technology Inc, 82P2282PF Datasheet - Page 76
82P2282PF
Manufacturer Part Number
82P2282PF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82P2282PF.pdf
(381 pages)
Specifications of 82P2282PF
Screening Level
Industrial
Pin Count
100
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
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3.18.1.4
modes. The offset is between the framing pulse on the TSFSn/MTSFS
pin and the start of the corresponding frame input on the TSDn/MTSD
IDT82P2282
Bit offset and channel offset are both supported in all the operating
Offset
Transmit Clock Master mode:
Transmit Clock Slave mode / Transmit Multiplexed mode:
Transmit Clock Slave mode / Transmit Multiplexed mode:
Transmit Clock Master mode:
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSD
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSD
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSD
TSFSn / MTSFS
TSCKn / MTSCK
TSDn / MTSD
Figure 28. No Offset When FE = 1 & DE = 1 In Transmit Path
Figure 29. No Offset When FE = 0 & DE = 0 In Transmit Path
F-bit of CH1 (T1/J1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
F-bit of CH1 (T1/J1)
F-bit of CH1 (T1/J1)
Bit 1 of TS0 (E1)
Bit 1 of TS0 (E1)
Bit 1 of TS0 (E1)
FE = 1, DE = 1
FE = 0, DE = 0
76
Bit 1 of CH1 (T1/J1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
Bit 1 of CH1 (T1/J1)
Bit 1 of CH1 (T1/J1)
Bit 2 of TS0 (E1)
pin. The signaling bits on the TSIGn/MTSIG pin are always per-channel
aligned with the data on the TSDn/MTSD pin.
Bit 2 of TS0 (E1)
Bit 2 of TS0 (E1)
DUAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Figure 28 to Figure 31 show the base line without offset.
Bit 2 (T1/J1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 3 (E1)
Bit 2 (T1/J1)
Bit 2 (T1/J1)
Bit 3 (E1)
Bit 3 (E1)
August 20, 2009
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