DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet
DJLXT6282LE.A3
Specifications of DJLXT6282LE.A3
Related parts for DJLXT6282LE.A3
DJLXT6282LE.A3 Summary of contents
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LXT6282 Octal E1 Digital Interface with CRC-4 Monitoring and Jitter/Wander Suppression LXT6282 is an eight-channel E1 digital interface. It integrates an E1 dejitter phase locked loop retiming function and a CRC-4 monitor function for each E1 transmitter and ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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... Insert/LOS Alarm filtering ...................................................25 3.1.10.4Frame Alignment/Out Of Frame Alarm......................................25 3.1.10.5CRC-4 Multiframe Alignment/Out of CRC Multiframe Alarm .....25 3.1.10.6CRC-4 Multiframe Monitoring....................................................25 3.1.10.7Test Pattern Generator for Autotesting/Maintenance................26 3.1.11 MICROCONTROLLER INTERFACE .....................................................26 3.1.11.1Intel Interface.............................................................................26 3.1.11.2Motorola Interface .....................................................................27 3.1.12 Iinterrupt Handling ..................................................................................27 3.1.12.1Interrupt Sources.......................................................................27 3.1.12.2Interrupt Enables .......................................................................27 3.1.12.3Interrupt Clearing.......................................................................28 3.1.12.4Status Registers Access ...........................................................28 3 ...
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LXT6282 4.1.5 CHIP_ID_NMB - Chip ID Number (4FH) ................................................ 32 4.1.6 BUFF_ALLCNT - Buffer All Counters (5FH)........................................... 33 4.1.7 E1_RCV_AISTAT - E1 Receivers AIS Status (8FH) .............................. 33 4.1.8 EI_XMT_AISTAT - E1 Transmitters AIS Status (9FH) ........................... 33 4.1.9 GLOB_CONF ...
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Figures 1 LXT6282 Block Diagram ....................................................................................... 7 2 LXT6282 Block Diagram ....................................................................................... 8 3 LXT6282 Block Diagram 2 ....................................................................................9 4 LXT6282 Pin Assignment....................................................................................10 5 Frame and Multiframe Acquisition....................................................................... outputs, transmitted to the LIUs, Timing ........................................................ inputs, ...
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LXT6282 Revision History Revision Date 6 Description Datasheet ...
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Figure 1. LXT6282 Block Diagram R e tim ...
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LXT6282 Figure 2. LXT6282 Block Diagram DRETCKREF DPLLCKREF ( High speed 65.536 MHz ADPLL reference Clock) DTC(i) DTC(i) (gapped Clock) Frame & S DTD(i) E1 DATA MultiFrame 2 (Data) Recovery P AIS Detect En Retiming elastic store Write CRC4 DTC(i) ...
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Figure 3. LXT6282 Block Diagram 2 DRETCKREF DPLLCKREF DTC0 DTD0 DTC1 DTD1 DTC2 DTD2 E1 DATA & DTC3 CLOCKS RECEIVED DTD3 FROM THE DEMULTIPLEXER (SXT6251) DTC4 DTD4 DTC5 DTD5 DTC6 DTD6 DTC7 DTD7 DATA[7..0] AD[7..0] WRB/RWB, RDB/E, ASB MCUTYPE, CSB ...
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LXT6282 1.0 Pin Assignments and Signal Descriptions Figure 4. LXT6282 Pin Assignment 1 DATA7 2 DATA6 3 DATA5 4 DATA4 5 GND_IO 6 VCC_IO 7 DATA3 8 DATA2 9 DATA1 10 DATA0 11 GND_3 12 VCC_3 ...
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Table 1. Signal Descriptions Pin Name Pin PROP E1 Transmitters (receive side of demultiplexer TPOSD<7...0> HiZ-4ma TNEGD<7...0> HiZ-4ma TCLK<7...0> HiZ-8ma ...
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LXT6282 Table 1. Signal Descriptions Pin Name Pin PROP DPLLCKREF 93 BUF- RPOSD<7...0> BUF- RNEGD<7...0> BUF- RLOS<7...0> BUF- ...
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... I Chip Select. Active low Address Strobe Enable. Indication that the address on the address bus is I valid. Active high. Motorola/Intel Interface mode select. A High indicates a Motorola and a I Low an Intel Microprocessor. I Chip Master Reset. A low will reset all registers to default values. Master chip output enable. Active high (a low will set all outputs and ...
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LXT6282 Table 1. Signal Descriptions Pin Name Pin PROP 12, 27, 52, VCC_3 71, 92, 96, 109, 127 11, 28, 53, GND_3 95, 108, 126 6, 37, 73, VCC_IO 107, 144 GND_IO 5, 36 106 1. Buf-in = ...
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... The LXT6282 integrates eight E1 transmitters and eight E1 receivers that can operate independently. It performs jitter/wander filtering, CRC-4 monitoring and HDB3 encoding/ decoding. It also includes a Motorola/Intel compatible microcontroller interface for alarm and performance monitoring. The following description follows the simplified block diagram (refer to 2 ...
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LXT6282 The degapped E1 output is emitted as NRZ data on TPOSD HDB3 encoded data on TPOSD and TNEGD. The dejittered and degapped output clock of each transmitter is emitted on TCLK at the same frequency as the ...
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If the Loss Of Signal alarm is active, the receiver may insert an AIS signal (all ones in the data), using the DRETCLK clock reference input as a blue clock. Data is fed to the framing/multiframing block that synchronizes the ...
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... Once the E1 frame is synchronized, the framer will go out of synchronization after three consecutive frame alignment signals containing single or multiple errors are received. In addition possible to configure the framing algorithm via register 0FH, so that the framer will also go out of synchronization if three consecutive bit 2 of the non- frame alignment signal are not one. A 12- bit microprocessor-accessible counter can be configured (see global register 0FH) to count either the errored FAS, the errored NFAS, or the FAS and the NFAS with single or multiple errors ...
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The multiframe consists of 16 basic E1 frames (eight double frames), numbered 0-15, that are further divided into two 8-frame sub-multiframes (SMF I and SMF II). Bit 1 of each frame is used to transport the Cyclic Redundancy Check bits, ...
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LXT6282 3.1.4 AIS Detection An AIS defect is detected in the DTDx input data when the incoming signal has two or less ZEROs in each of two consecutive double frame periods (512 bits). This defect alarm is cleared when each ...
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If the read system clock (DRETCKREF) frequency is lower than the write incoming clock (DTCx) frequency, then when the FIFO is close to overflow, the read control logic will perform a slip of one complete frame. This results in the ...
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LXT6282 Figure 5. Frame and Multiframe Acquisition Frame Acquisition 3 consecutive incorrect NFAS and 3 consecutive 4 consecutive CnfFaOp[1,0]=01 incorrect FAS incorrect FAS and and CnfFaOp[1,0]=0X CnfFaOp[1,0]=1X Desync CRC MF OUT OF MULTIFRAME (LOMF Alm) => Desync CRC MF (if ...
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A maskable interrupt is also provided to indicate the inoperability of the elastic store. This alarm indicates that the clock frequencies are so different that slippage is continual. By setting a special configuration in register iEH, the transmit retiming 2 ...
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LXT6282 The relative phase between output data and clock can be configured via microprocessor (TPOSDx/ TNEGDx data outputs emitted on rising or falling edge of the output clock TCLKx: see global register AFH). Depending on the transmitter configuration, TCLK transmit ...
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The AIS defect alarm status is accessible to the microprocessor via the status registers. 3.1.10.3 AIS Insert/LOS Alarm filtering This block includes a filter for Loss Of Signal Alarm input on RLOS pin from the external LIU. The filtering on ...
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... The microprocessor interface is a generic asynchronous interface, including an address bus (A [7..0]), data bus (DATA [7..0]) and handshaking pins (WRB/RWB, RDB/E, CSB, and ALE). The MCUTYPE input pin indicates the type of microprocessor interface to be used – Intel or Motorola. There is also an INT output pin that indicates status changes to the microprocessor. ...
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Both cycles require the CSB pin to be LOW and the uP to drive the A[7..0] address pins. In the case of the write cycle, the uP is also required to drive the DATA [7..0] data pins. In the case ...
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LXT6282 3.1.12.3 Interrupt Clearing In the discussion below it is assumed that the example interrupt sources have their interrupt enable bits SET. Status change interrupt sources have their interrupt bits cleared when their status is read. For example, say the ...
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Microprocessor Register Description The address mapping (8 address bits) is the following: • addresses 0FH -> AFH: Global registers • addresses i1H -> iEH: transmitter registers ( and channel number) • addresses ...
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LXT6282 Address Mnemonic j9-j8H REC_BLCK_ERC jB-jAH REC_RMT_BLCK_ERC jD-jCH REC-CD_ERC 4.1 Global Registers The registers described in this section are related to global configuration, tests and alarms. 4.1.1 GLOB_CONF0 - Global Operational Configuration 0 (0FH) Configures high level operational characteristics of ...
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Bit Name These bits configure the Bipolar Violation Errors Detection in all the E1 HDB3 receivers (on RPOSD and RNEGD inputs, from the LIU Disable Bpv Detection Bit CnfBpvDet[1.. consecutive ‘1’ with the same polarity ...
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LXT6282 Bit Name This bit configures the generation of the test pattern sequence as framed or unframed (both test pattern sequences are described in 0.151) Bit 2 AutotestCnfg 0 - Unframed (PBRS2E15-1 sequence CRC-4 framed sequence. The PRBS2E15-1 ...
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BUFF_ALLCNT - Buffer All Counters (5FH) A write to this location causes all of the counters of the same type to be loaded into buffers and then cleared. This operation assumes that those counters can be monitored in the ...
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LXT6282 4.1.9 GLOB_CONF - Global Operational Configuration 3 (AFH) Bit Name Bit 7 CnfTxClkIn Bit 6 CnfTxClkOut Bit 5 CnfRxClkIn Bit 4 CnfRxClkOut Bit DjtAisSetWinNum[3:0] <3:0> 4.2 Transmit Side Registers The registers described in this section are related to the ...
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Interrupt source: This register set will identify the alarm(s) that triggered the interrupt. • Alarm status: This register contains the current status of the alarm. When this register is read, the corresponding interrupt will be cleared. • Interrupt Enable: ...
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LXT6282 Bit Name Enable/disable G704 CRC-4 monitoring and multiframing in the E1 transmitter (on DTD data input Disable. In this case, the E1 transmitter checks the errors in the E1 Bit 3 XmtCrc-4En frameword (every two frames) and ...
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Bit Name Indicates that a positive frame slip has occurred in the retiming elastic Bit 7 XmtPosSlip buffer cleared when this register is read. Indicates that a negative frame slip has occurred in the retiming elastic Bit 6 ...
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LXT6282 4.2.5 XMT_ALM_INTE0 - Transmitter Alarm Interrupt Enable 0 (i4H and corresponds to the E1 channel number) This register can be used to enable an interrupt source for a particular E1 channel interrupt source. The ...
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Bit Name Bit <15:13> Unused Bit <12:0> XmtFasErrCnt[12:0] 4.2.8 XMT_BLCK_ERC - Transmitter CRC-4 Block Errors Counter (i9H - i8H and corresponds to the E1 channel number) (i9H = bits<15:8>, i6H = bits<7:0> This counter increments ...
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LXT6282 Bit Name Bit <7:4> RetNegCnt[3:0] Bit <3:0> RetPosCnt[3:0] 4.2.11 XMT_RTMBUF_STAT - Transmitter Retiming Buffer Status (iDH and corresponds to the E1 channel number) A write to the register (register iDH) causes the Retiming elastic ...
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Interrupt Enable: This register contains the interrupt enables for all alarms Status alarms will generate an interrupt both when the alarm changes from inactive to active or active to inactive. The overflow alarms generate an interrupt when detected. Updating ...
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LXT6282 4.3.2 RCV_ALRM_INT0 - Receiver Alarm Interrupt 0 (j1H and corresponds to the E1 channel number) This register identifies the interrupt source for a particular E1 channel receiver. Each of these bits can cause the chip ...
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These registers are associated with the interrupt source registers. Status interrupt source bits have an associated status bit. Generally, when an interrupt is being acknowledged, the status bit will be checked to see the present status of the interrupt-generating source. ...
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LXT6282 Bit Name Bit Unused <7:4> Bit 3 BpvOvrFlwIntEn Bit 2 RcvRbeOvrFlwEn Bit 1 RcvCrcOvrFlwIntEn Bit 0 RcvFasErrOvrFlwEn 4.3.7 RCV_FRMWD_ERC - Receiver FrameWord Error Counter (j7 - j6H and corresponds to the E1 channel number) (j7H ...
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This counter increments each time a remote CRC-4 block error is detected. A write to the MSByte of the counter (Register jBH) causes the entire counter to be buffered and then cleared. The contents of the buffer can then be ...
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LXT6282 5.0 Test Specifications Table 4. Absolute Maximum Ratings Parameter Supply Voltage 1 DC Voltage on any pin Ambient operating temperature Storage temperature range 1. Minimum voltage is -0.6V dc which may undershoot to -1.0 V for pulses of less ...
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Figure 6. E1 outputs, transmitted to the LIUs, Timing DRETCKREF t TCKOpd TCLKi t TDOpd TPOSDi TNEGDi Global Conf. Register @ 0xAF / bit #6 : Table 7. E1 outputs, transmitted to the LIUs, Timing Parameters Parameter DRETCKREF rising edge ...
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LXT6282 Figure 8. E1 inputs, received from the demultiplexer, Timing DTCi t t RDIsu DTDi Global Conf. Register @ 0xAF / bit #7 : Table 9. E1 inputs, received from the demultiplexer, Timing Parameters Parameter DTDi setup time to DTCi ...
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... Figure 10. Microprocessor Read Timing MicroProcessor Read Timing (Intel Mode) t SAR A<7:0> t SALR t t HALR VL ASB t SCR CSB t SLR t VRD RDB INT t DDR DATA<7:0> t ADR t AAC t AAC Table 11. Microprocessor Data Read Timing Parameters (considering outputs with a 50pF load) Parameter A<7:0> setup time to read cycle end A< ...
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... Inactive read to inactive INT (due to reset on read feature) 1. For non-multiplexed Address and Data bus ( 2. For multiplexed Address and Data bus ( the minimum cycle time of either DTCi, either, DRETCKREF, or MTCi (typically 488 ns for E1) Figure 11. Microprocessor Write Timing MicroProcessor Write Timing (Intel Mode) t SAW A<7:0> t SALW ...
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Table 12. Microprocessor Data Write Timing Parameters Parameter RWB setup to active write RWB hold from inactive write CSB setup to active write CSB hold from inactive write DATA<7:0> setup to inactive write DATA<7:0> hold from inactive write Valid write ...
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LXT6282 6.0 Testability The LXT6282 provides a method for enhancing testability: IEEE1149.1 Boundary Scan (JTAG) is used for testing of the interconnect. 6.1 IEEE 1149.1 Boundary Scan Description The boundary scan circuitry allows the user to test the interconnection between ...
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Instruction Register and Definitions The LXT6282 supports the following instructions IEEE1149.1: EXTEST, SAMPLE/PRELOAD, BYPASS and IDCODE. Instructions are shifted into the instruction register during the SHIFT-IR state and become active upon exiting the UPDATE-IR state. The instruction register definition ...
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LXT6282 6.1.1.4 IDCODE (‘b10) This instruction allows the reading of component types via the scan chain. During this instruction, the 32-bit Device Identification Register (ID-Register) is placed between TDI and TDO. The ID Register captures a fixed value of (‘h ...
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Figure 13. Boundary Scan Cell Data in Scan in Shift dr Clock dr Data in Scan in Shift dr Clock dr Update dr Mode Table 14. Boundary Scan Order dpllckref Clock mcutype Data scanen Data scantest Data dretckref Clock oen ...
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LXT6282 Table 14. Boundary Scan Order dtd[6] Data dtc[6] Data dtc[5] Data dtd[5] Data mtd[5] Data mtc[5] Data mtc[4] Data mtd[4] Data dtd[4] Data dtc[4] Data dtc[3] Data dtd[3] Data mtd[3] Data mtc[3] Data mtc[2] Data mtd[2] Data dtd[2] Data ...
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Table 14. Boundary Scan Order data/o[1] Data data/i[0] Data data/o[0] Data oen_c Enble rdb_c Enble a[7] Data a[6] Data a[5] Data a[4] Data a[3] Data a[2] Data a[1] Data a[0] Data csb Data asb Data wrb Data rdb Data reset ...
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LXT6282 Table 14. Boundary Scan Order tclk[3] Data rlos[2] Data rnegd[2] Data rposd[2] Data rclk[2] Data tnegd[2] Data tposd[2] Data tclk[2] Data tclk[5] Data tposd[5] Data tnegd[5] Data rclk[5] Data rposd[5] Data rnegd[5] Data rlos[5] Data tclk[4] Data tposd[4] Data ...
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Glossary AIS Alarm Indication Signal FAS E-1 Frame Alignment Signal FIFO First in/First Out Memory MFAS E1 CRC-4 Multiframe Alignment Signal NFAS E1 Non-Frame Alignment Signal PDH Synchronous Digital Hierarchy SDH Synchronous Digital Hierarchy Datasheet LXT6282 59 ...
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LXT6282 8.0 Package Information D/2 E1/2 E1 144-pin L Quad Flat Pack package (1.40 mm body thickness) 1 Dimension See JEDEC Publication for additional specifications NOTE: ...