S1212PB20 Applied Micro Circuits Corporation, S1212PB20 Datasheet

S1212PB20

Manufacturer Part Number

S1212PB20

Description

Manufacturer

Applied Micro Circuits Corporation

Datasheet

1.S1212PB20.pdf (2 pages)

Specifications of S1212PB20

Operating Supply Voltage (typ)

2.5V

Operating Supply Voltage (max)

3.3V

Mounting

Surface Mount

Pin Count

196

Lead Free Status / RoHS Status

Not Compliant

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Bonase Electronics (HK) Co., Limited

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S1212PB20

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AMCC

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S1212

SONET/SDH/ATM Quad OC-3/12 with Clock Data Recovery (CDR)

Description

The S1212 device consists of four CDR

modules. Each of the modules can

independently run at the OC-12 or OC-3

data rate. The S1212 can also be

provisioned to mix and match OC-3 and

OC-12 data streams within the same

device. The S1212 can be configured in

MII (Media Independent Interface) mode

or in Non-MII mode.

The S1212 minimizes the external

components on the board:

no external loop filter component,

internally biased outputs,

internally provided common mode bias

for AC input, and internally provided bias

for external LVPECL driver.

The S1212 offers significant advantages

in power and real estate with high

integration, low power, and a small

package.

With Integrated

SERDES

Framers

ASIC

CLOCK

DATA

CDR

Overview

The function of the S1212 clock and data

recovery unit is to derive high speed tim-

ing signals for SONET/SDH-based

equipment. The S1212 receives either

an OC-12 or an OC-3 scrambled NRZ

signal and recovers the clock from the

data stream. The device outputs a differ-

ential bit clock and retimed data. Figure

1 shows a typical network application.

The Low Voltage Differential Signaling

(LVDS) or LVPECL interfaces guarantee

compliance with the bit-error rate

requirements of the Telecordia and ITU-

T standards.

AMCC Suggested Interface Devices

AMCC

Agilent

Infineon

Agere

Sumitomo

OCP

MII port

S1212

Figure 1. System Block Diagram

DATA

S4805

S4806

S1208

HFBR-5908E

V23818-H18

1417G4A

SCM7101-XC

DTR-156-5M

DANUBE

OHIO

EVROS

OTX

ORX

SONET/SDH Mapper

STS-48/STM-16,

4 x STS-12/STM-

4 x STS-3/STM-1

0C-48/4 x OC-12

SONET/SDH Framer

and channelized ATM/

POS Mapper

STS-12/STM-4 DS3/

E3/DS1 E1/VT/TU

SONET/SDH Mapper

Optical Transceiver

OTX

Optical Transceiver

OTX

DATA

MII port

S1212

CDR

CLOCK

CDR

CLOCK

CDR

CLOCK

CDR

DATA

CDR

DATA

CDR

DATA

CDR

DATA

CDR

CLOCK

General Features

• CMOS 0.13 micron technology

• Complies with Bellcore and ITU-T

• On-chip high-frequency PLLs for

• Supports Data Rates of 155.52

• LVDS or LVPECL differential

• Internal termination of the optic’s

• Typical 350 mW power in LVDS

• Directly compatible with 2.5 V or

• 196 Ball Grid Array Package

• 1.2 V and 3.3 V/2.5 V Power

Continued on next page...

With integrated

specifications for jitter tolerance,

jitter transfer, and jitter generation

clock generation and clock

recovery

Mbps (OC-3) and 622.08 Mbps

(OC-12)

serial interface

LVPECL driver renders a

seamless power saving

connection

I/O mode

3.3 V LVDS, 3.3 V LVPECL (DC

and AC)

supply

–

SERDES

Framer

ASIC

A t a G l a n c e

PB1622_v1.01_01/23/04

Product Brief

–

Related parts for S1212PB20

S1212PB20 Summary of contents

Page 1

S1212 SONET/SDH/ATM Quad OC-3/12 with Clock Data Recovery (CDR) Description The S1212 device consists of four CDR modules. Each of the modules can independently run at the OC-12 or OC-3 data rate. The S1212 can also be provisioned to mix ...

Page 2

S1212 SONET/SDH/ATM Quad OC-3/12 with Clock Data Recovery (CDR) The sequence of operations is as follows for each Channel: 1. Serial data input 2. Serial Data and recovered clock outputs Internal clocking and control functions are transparent to the user. ...

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