PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet
PEF81902FV1.1
Specifications of PEF81902FV1.1
Related parts for PEF81902FV1.1
PEF81902FV1.1 Summary of contents
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Edition 2001-11-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms ...
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PEF 81902 Revision History: Previous Version: Page Subjects (major changes since last revision) Table 18 Additional C/I-command LTD Figure 34 Chapter 2.4.7.4 Chapter 3.2.3 The Framer / Deframer Loopback (DLB more supported Chapter 4.3 Chapter 4.9.4 Chapter 4.3 ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.4.4.2 Block Error Counter (RDS Error Counter 2.4.5 Scrambler / Descrambler . . . . ...
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Table of Contents 3.1.5 Complete Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.4.21 CIX1 - Command/Indication Transmit 162 4.5 Detailed S-Transceiver Registers . . ...
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Table of Contents 4.9.3 UCIW - C/I Code Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 ...
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List of Figures Figure 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 41 State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 83 NTC-Q Compatible State Machine Q-SMINT‚IX: 2B1Q . . . . . . . . . . . 217 Figure 84 Simplified State Machine Q-SMINT‚IX: 2B1Q . . . . . . . . . . ...
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List of Tables Table 1 NT Products of the 2nd Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ...
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List of Tables Table 42 Parameters of the UVD/POR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 210 Table 43 Design Number ...
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Overview The PEB 81902 (T-SMINT which ease the realization of an intelligent NT. â The T-SMINT IX features U-transceiver, S-transceiver, HDLC controller and an IOM 2 interface on a single chip. A microcontroller interface provides access to both transceivers, ...
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References [1] TS 102 080, Transmission and Multiplexing; ISDN basic rate access; Digital transmission system on metallic local lines, ETSI, November 1998 [2] FTZ 1 TR 220 Technische Richtlinie, Spezifikation der ISDN Schnittstelle Uk0 Schicht 1, Deutsche Telecom AG, ...
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Second Gen. Modular ISDN NT (Intelligent eXtended) ® T-SMINT IX Version 1.1 1.2 Features Features known from the PEB 8090 • U-transceiver and S-transceiver on one chip • U-interface (4B3T) conform to ETSI [1] and FTZ [2] : – ...
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Siemens/Intel multiplexed – Motorola – programmable MCLK (can be disabled) â • Enhanced IOM interface – Timeslot access and manipulation – BCL output; programmable and flexible strobes SDS1/2, e.g. active during several timeslots. – Optional: All registers can be ...
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Pin Configuration • /VDDDET 49 50 VDDa_SR 51 52 VSSa_SR XOUT 59 XIN 60 BOUT ...
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Block Diagram • SR1 SR2 SX1 S-Transceiver SX2 TP1 Factory Tests TP2 IOM-2 Interface FSC DCL BCL DU DD Figure 2 Block Diagram Data Sheet XIN XOUT RST RSTO VDDDET Clock Generation POR/UVD D-Channel Arbitration HDLC M Controller O ...
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Pin Definitions and Functions • Table 2 Pin Definitions and Functions Pin Symbol VDDa_UR 2 VSSa_UR 1 VDDa_UX 62 VSSa_UX 63 VDDa_SR 51 VSSa_SR 52 VDDa_SX 46 VSSa_SX 45 VDDD 29 VSSD 30 VDDD 13 VSSD 14 FSC 32 ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol SDS1 8 SDS2 SCLK 26 AD5 26 SDR 27 AD6 27 Data Sheet Type Function O Serial Data Strobe1: Programmable strobe signal for time slot and/or D-channel indication ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol SDX 28 AD7 28 AD0 21 AD1 22 AD2 23 AD3 24 AD4 ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol 10 WR R/W ALE 9 RST 5 RSTO 6 INT 15 MCLK 18 EAW 20 SX1 43 SX2 44 SR1 47 Data Sheet Type Function I Write Indicates a write access ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol SR2 48 XIN 60 XOUT 59 AOUT 64 BOUT 61 AIN 3 BIN 4 VDDDET 49 ACT 17 TP1 42 TP2 50 16, 19, 41, 55 res 56, 57 ...
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I: Input O: Output (Push-Pull) OD: Output (Open Drain) 1.6.1 Specific Pins and Test Modes LED Pin ACT A LED can be connected to pin ACT to display four different states (off, slow flashing, fast flashing, on). It displays the ...
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System Integration • S/T - Interface POTS Interface HV - SLIC SLICOFI SLIC Figure 3 Application Example T-SMINT The U-transceiver, the S-transceiver, the IOM be controlled and monitored via: a) the parallel or serial microprocessor interface - ...
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IOM-2 Slave e.g. SLICOFI-2 Figure 4 Control via µP Interface Alternatively, the T-SMINT â b) the IOM -2 Interface - Access of on-chip registers via the Monitor channel with Header/Address/Data format (Device is Monitor slave) - Activation/Deactivation control of ...
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S IOM -2 IOM-2 Master e.g. UTAH Figure 5 Control via IOM Data Sheet C/I1 C/I0 MON INT â -2 Interface 15 PEF 81902 Overview U Register iomslave.vsd 2001-11-12 ...
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Functional Description 2.1 Microcontroller Interfaces â The T-SMINT IX supports either a serial or a parallel microcontroller interface. For applications where no controller is connected to the T-SMINT interface, register programming is done via the IOM master device. In ...
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The T-SMINT edge of SCLK and shifts out at the falling edge of SCLK. Each access must be terminated by a rising edge of CS. Data is transferred in groups of 8 bits ...
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Write Access CS SCLK SDR SDX Read Access CS SCLK SDR SDX Figure 6 Serial Control Interface Timing Data Sheet Command/Address Header ...
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Programming Sequences The basic structure of a read/write access to the T-SMINT control interface is shown in • write sequence: header SDR 7 read sequence: header SDR 7 SDX Figure 7 Serial Command Structure A new programming sequence starts ...
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Example for a read/write access with header 40 SDR header wradr SDX Header 48 : Interleaved A-D-A-D Sequences H The interleaved A-D-A-D sequences give direct read/write access to the address range 00 -7F ...
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H reception of the wradr. The sequence can have any length and is terminated by the rising edge of CS. Example for a read/write access with header 41 SDR header rdadr SDX Header 49 : ...
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A read/write access to the T-SMINT multiplexed mode. In non-multiplexed mode the register address must be applied to the address bus (A0- A6) for the data access via the data bus (D0-D7). In multiplexed mode the address on the address ...
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Direct Address Mode AMOD = ´1´ 7Fh 7Eh 7Dh 7Ch 04h 03h 02h 01h 00h Figure 8 Direct/Indirect Register Address Mode 2.1.3 Microcontroller Clock Generation The microcontroller clock is derived from the unregulated 15.36 MHz clock ...
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Reset Generation Figure 9 shows the organization of the reset generation of the T-SMINT •. 125µs C/I0 Code Change (Exchange Awake 125µs Watchdog Software Reset Register (SRES) RES_CI Reset RES_HDLC Functional Block RES_S RES_U Internal Reset of ...
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The internal reset sources set the MODE1 register to its reset value. Table 8 Reset Source Selection RSS2 RSS1 Bit 1 Bit POR/UVD can be enabled/disabled via pin VDDDET • ...
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External Reset Input At the RST input an external reset can be applied forcing the T-SMINT state. This external reset signal is additionally fed to the RSTO output. After release of an external reset, the C has to wait for ...
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IOM -2 Interface â The T-SMINT IX supports the IOM â according to the IOM -2 Reference Guide [12]. â 2.3.1 IOM -2 Functional Description â The IOM -2 interface consists of four lines: FSC, DCL, DD, DU and ...
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The frame is composed of three channels: • Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR programming channel (MON0) and a command/indication channel (CI0) for control and programming of e.g. the U-transceiver. • Channel ...
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Figure 11 Architecture of the IOM Data Sheet Functional Description CDA Data Monitor Data TIC Bus Data C/I0 Data C/I1 Data D Data D/B1/B2 Data C/I0 Data â -2 Handler 29 PEF 81902 DU DD FSC DCL BCL/SCLK SDS1 ...
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Controller Data Access (CDA) The four controller data access registers (CDA10, CDA11, CDA20, CDA21) provide microcontroller access to the 12 IOM • looping four independent PCM channels from vice versa over the ...
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TSa 1 0 Enable output (EN_O0) CDAx0 1 0 TSa a,b = 0...11 Figure 12 Data Access via CDAx0 and CDAx1 register pairs Looping and Shifting Data Figure 13 gives examples for typical configurations ...
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Looping Data .TSS: .DPS .SWAP b) Shifting Data TSa CDA10 .TSS: TSa .DPS .SWAP c) Switching Data TSa CDA10 TSa .TSS: .DPS .SWAP Figure 13 Examples for Data Access via CDAxy Registers a) Looping Data b) Shifting (Switching) ...
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Figure 14 shows the timing of looping TSa from via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD. Figure 15 shows the timing of shifting data ...
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Shifting TSa TSb within one frame (a,b: 0...11 and b a+2) FSC DU TSa (DD) CDAxy b) Shifting TSa TSb in the next frame (a,b: 0...11 and ( <a) FSC DU TSa (DD) CDAxy ...
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Monitoring Data Figure 16 gives an example for monitoring of two IOM simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the channel registers ...
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CRx. The TSDPx0 must be set for monitoring from DD. By this it is possible to monitor the TIC bus (TS11) and h the odd numbered D-channel (TS3) simultaneously on DU ...
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Table 9 Examples for Synchronous Transfer Interrupts Enabled Interrupts (Register MSTI) STI STOV ...
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INT CIC CIC TIN TIN WOV WOV S S MOS MOS HDLC HDLC MASK ISTA Figure 17 Interrupt Structure of the Synchronous Data Transfer Figure 18 shows some examples based on the timeslot structure. Figure ...
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STI interrupt generated : STOV interrupt generated for a not acknowledged STI interrupt a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: TS11 b) Interrupts for data ...
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Serial Data Strobe Signal For time slot oriented standard devices at the IOM provides two independent data strobe signals SDS1 and SDS2. The two strobe signals can be generated with every 8-kHz-frame and are controlled by the registers SDS1/2_CR. ...
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Figure 19 shows three examples for the generation of a strobe signal. In example 1 the SDS is active during channel B2 on IOM and MON1. The third example shows a strobe signal for 2B+D channels which is used e.g. ...
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The MONITOR channel protocol is described In the following section and shall illustrate this. The relevant control and status bits for transmission and reception are listed in Table 10 and Table 10 Transmit Direction Control/ Register Status Bit Control MOCR ...
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P µ MIE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 MDA Int. MOX = DATA2 MDA Int. MXC = 0 MAC = 0 Figure 20 MONITOR Channel Protocol (IOM Before ...
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MONITOR channel interrupts by setting MONITOR Interrupt Enable (MIE) to ’1’ result, the first MONITOR byte is acknowledged by the receiving device setting the MR bit to ’0’. This causes a MONITOR Data Acknowledge MDA ...
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Since a double last-look criterion is implemented the receiver is able to receive the MON slot data at least twice (in two consecutive frames), the receiver waits for the acknowledge of the reception of two identical bytes in two ...
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IOM -2 Frame No. MX (DU) MR (DD) Figure 21 Monitor Channel, Transmission Abort requested by the Receiver • IOM -2 Frame No. MR (DU) MX (DD) Figure 22 Monitor Channel, Transmission Abort requested by the Transmitter • IOM ...
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MONITOR Channel Programming as a Master Device The master mode is selected by default if one of the microcontroller interfaces is selected. The monitor data is written by the microcontroller in the MOX register and â transmitted via IOM ...
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DU 1st byte value DU 2nd byte value DU 3rd byte value DU 4th byte value DU (nth + 3) byte value All registers can be read back when setting the R/W bit to ’1’. The T-SMINT â by ...
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MASK U ST CIC TIN WOV S MOS HDLC INT Figure 24 MONITOR Interrupt Structure 2.3.4 C/I Channel Handling The Command/Indication channel carries real-time status information between the T- â SMINT IX and another device connected to the IOM ...
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In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to “1” and 6-bits are read whereby only the 4 LSBs are used for comparison and interrupt generation (i.e. the higher two bits are ignored). The ...
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D-Channel Access Control The upstream D-channel is arbitrated between the S-bus, the internal HDLC controller and external HDLC controllers via the TIC bus (S/G, BAC, TBA bits) according to the â IOM -2 Reference Guide to set the priority ...
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D-channel HDLC controller (transmission of an HDLC frame in the D- channel). A software access request to the bus is effected by setting the BAC bit in register CIX0 to ’1’ (resulting in BAC = ’0’ on ...
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Stop/Go Bit Handling The availability of the DU D channel is indicated in bit 5 "Stop/Go" (S/G) of the last octet in DD channel 2 (Figure MODEH.DIM2-0=0x1. S stop S The Stop/Go ...
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The configuration settings of the T-SMINT summarized in Table 12. • â Table 12 T-SMINT IX Configuration Settings in Intelligent NT Applications Functional Configuration Block Description Layer 1 Select Intelligent NT mode Layer 2 Enable S/G bit and TIC bus ...
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D=0) & [BAC = 1 or (BAC = 0 & CNT BAC = d.c. DCI = 0 S ACCESS S Setting DCI = 1 causes ...
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T-SMINT IX S-transceiver transmits inverted echo channel (E bits) on the S-bus to block all connected S-bus terminals (E = D). • Local D-channel source commences with D data transmission on IOM it receives S/G = “0”. • After ...
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FSC DI DIN DR DOUT b) DCL DIN D Figure 30 Deactivation of the IOM Conditions for Power-Down If none of the following conditions is true, the IOM reducing power consumption to a minimum. • S-transceiver is not ...
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U-Transceiver The statemachine of the U-Transceiver is compatible to the NT state machine in the PEB 8090 documentation [9], but includes some minor changes for simplification and compliance to Ref. [1]. The U-transceiver is configured and controlled via the ...
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data • 11 symbols: Barker code for both symbol and frame synchronization (not scrambled) • 1 symbol: Ternary maintenance symbol (not scrambled) The 108 user data symbols ...
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D ... D Ternary data of IOM Maintenance symbol +, – Syncword Data Sheet Functional Description ® -2 frames 1 ... 8 60 PEF 81902 2001-11-12 ...
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Table 14 Frame Structure B for Upstream Transmission 1/2 1/2 1 ...
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Maintenance Channel The 4B3T frame structure provides a 1 kbit/s M(aintenance)-channel for the transfer of remote loopback commands and error indications. Loopback Commands The LT station uses the M-channel to request remote loopbacks. Loopback commands are coded with a ...
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Table 15 MMS 43 Coding Table (cont’ – ...
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Table 16 4B3T Decoding Table (cont’ – 0 – – – 2.4.4.1 Monitoring of Code Violations The running digital sum monitor (RDSM) computes the running digital sum from the received ...
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Note that every frame with a detected code violation causes about binary bit errors on average bit error rate of 10 frame errors within 1000 s in the LT (1 frame error detected in the ...
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C/I code ‘1010‘ must not be input to the U-transceiver. • AI Activation Indication AIL Activation Indication Loop 2 AR Activation Request ARL Activation Request Local ...
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Figure 31 State Diagram Example Each state has one or more transitions to other states. These transitions depend on certain conditions which are noted next to the transition lines. These conditions are the only possibility to leave a state. If ...
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LT INFO U2W 2.133 ms NT Figure 32 Awake Procedure initiated by the LT • INFO U1W 2.133 ms Figure 33 Awake Procedure initiated by the NT Acting as Calling Station After sending the awake signal, the ...
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Acknowledging a Wake-Up Call If a deactivated device detects an awake signal acknowledge signal is sent out. After that, the U-transceiver waits for a possible repetition of the awake signal (in case the acknowledge hasn’t been recognized). ...
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NT State Machine (IEC-T / NTC-T Compatible) • T6S T6E T13E Ack. Sent / Received T12S U1A (U0 & T12E) Synchronizing RSY SBC Synchronizing LOF AR / ARL Wait for Info U4H LOF ...
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Table 19 Differences to the former NT-SM of the IEC-T/NTC-T No. State/ Signal Change 1. State ’Deact. split into 3 states Request Rec.’ - ’Pend. Deactivation 1’ - ’Reset’ State - ’Test’ State 2. State ’Loss of new inserted, ...
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RES Reset Unconditional command which resets the U-transceiver. SSP Send Single Pulses Unconditional command which requests the transmission of single pulses on the U-interface. TIM Timing The U-transceiver is requested to enter state ’IOM Awaked’. U-Interface Events U0 U0 detected ...
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Table 20 Timers (cont’d) Timer Duration (ms) T12 12 T13 13 2.4.7.5 Outputs of the U-Transceiver Below the signals and indications are summarized that are issued on IOM indications) and on the U-interface (predefined U-signals). C/I Indications AI Activation Indication ...
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RSY Resynchronizing Indication RSY informs the downstream device that the U-transceiver is not synchronous. Signals on U-Interface The signals U0, U1W, U1A, U1, U3, U5 and SP are transmitted on the U-interface.They are defined in Table 29. ® Signals on ...
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Acknowledge Sent / Receive After having sent the awake signal, the U-transceiver has received the acknowledge wake tone. If being awoken the U-transceiver has sent the acknowledge. In both cases the U-transceiver waits for possible repetition or time-out. Awake Signal ...
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Start Awaking Uk0 On the receipt the C/I-channel the U-transceiver sends the awake signal U1W to start an activation. Synchronizing After the successful awake procedure the U-transceiver trains its receiver coefficients until it is able to detect ...
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UCIR C/I C/I C/I 0 C/I intstruct_4b3t.emf Figure 35 Interrupt Structure U-Transceiver Data Sheet ISTAU MASKU RDS RDS 1ms 1ms 0 ...
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S-Transceiver The S-Transceiver offers the NT and LT-S mode state machines described in the User’s Manual V3.4 [8]. The S-transceiver lies in IOM via the registers described in but can be set to LT-S mode via register programming. The ...
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Figure 37 Frame Structure at Reference Points S and T (ITU I.430) – F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N ...
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S/Q Channels, Multiframing According to ITU recommendation I.430 a multi-frame provides extra layer-1 capacity in the TE-to-NT direction through the use of an extra channel between the TE and NT (Q- channel). The Q bits are defined to be ...
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S data will be inserted at the downstream (NT (see Table 24). Access to S2-S5-channel is not supported. Interrupt Handling for Multi-Framing To trigger the microcontroller for a multi-frame access an interrupt can be generated once per multi-frame (SQW) or ...
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C/I Command IOM-2 C/I Indication Figure 38 S-Transceiver Control The state diagram notation is given in The information contained in the state diagrams are: – state name – Signal received from the line interface (INFO) – Signal transmitted to ...
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IOM-2 Interface C/I code S/T Interface INFO Figure 39 State Diagram Notation As can be seen from the transition criteria, combinations of multiple conditions are possible as well. A “ ” stands for a logical AND combination. And a ...
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C/I Codes in Reset State In the reset state the C/I code 0000 (TIM) is issued. This state is entered either after a hardware reset (RST) or with the C/I code RES. C/I Codes in Deactivated State If the S-transceiver ...
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Receive Infos on S/T I0 INFO 0 detected I0 Level detected (signal different to I0) I3 INFO 3 detected I3 Any INFO other than INFO 3 Transmit Infos on S/T I0 INFO 0 I2 INFO 2 I4 INFO 4 It ...
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State Machine NT Mode • RST TIM RES DR Reset i0 * RES DC Any State AID RSY ARD i3*ARD G2 Lost Framing S/T i3*AID i2 i3 RSY DR ARD 2) AID RSY RSY G3 Lost Framing U i2 ...
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G1 Deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOM G1 I0 Detected An ...
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G4 wait for DR Final state after a deactivation request. The S-transceiver remains in this state until DC is issued. Unconditional States Test Mode TM1 Send Single Pulses Test Mode TM2 Send Continuous Pulses C/I Commands • Command Abbr. Deactivation ...
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Command Abbr. Activation Indication AIL Loop Deactivation DC Confirmation Indication Abbr. Timing TIM Receiver not RSY Synchronous Activation Request AR Illegal Code Ciolation CVR Activation Indication AI Deactivation DI Indication Data Sheet Code Remark 1110 Activation Indication Loop 1111 Deactivation ...
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State Machine LT-S Mode • RST TIM RES DR Reset i0 * RES DC Any State DC RSY ARD i3 G2 Lost Framing S ARD = AR or ARL Figure 41 State Machine LT-S ...
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G1 deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOM G2 pending activation As ...
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Test mode - TM2 Continuous alternating pulses are sent on the S/T-interface. • Command Abbr. Deactivation Request DR Reset RES Send Single Pulses TM1 Send Continuous TM2 Pulses Activation Request AR Activation Request ARL Loop Deactivation DC Confirmation Indication Abbr. ...
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S-Transceiver Enable / Disable The layer-1 part of the S-transceiver can be enabled/disabled with the two bits S_CONF0.DIS_TR and S_CONF2.DIS_TX. If DIS_TX=’1’ the transmit buffers are disabled. The receiver will monitor for incoming data in this configuration. By default ...
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Interrupt Structure S-Transceiver • S_STA 7 RINF 0 FECV 0 FSYN SQRR MSYN 7 MFEN 0 0 SQR1 SQR2 SQR3 0 SQR4 SQXR 7 0 MFEN 0 0 SQX1 SQX2 SQX3 0 SQX4 Figure 42 Interrupt ...
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HDLC Controller â The T-SMINT IX contains a HDLC controller which can be used for the layer-2 functions of the D- channel protocol (LAPD) or B-channel protocols. By setting the enable HDLC channel bits (EN_D, EN_B1H, EN_B2H) in the ...
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Characteristics: no address recognition Every received frame is stored in RFIFO (first byte after opening flag to CRC field). Additional information can be read from RSTA. Transparent mode 1 (MDS2-0 = ’111’). Characteristics: SAPI recognition A comparison is performed on ...
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RPF (Receive Pool Full) interrupt, indicating that a data block of the selected length (EXMR.RFBS) can be read from RFIFO. The message which is currently received exceeds the block size so further blocks will be received to complete the ...
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RBCL contain the number of valid bytes in the last data block indicated by RME (length of last data block the number of bytes in the last data block or number of complete data blocks, respectively. If the ...
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RAM EXMR.RFBS=11 so after the first 4 bytes of a new frame have been stored in the fifo a receive pool full interrupt ISTAH.RPF is set. HDLC Receiver µP RAM HDLC Receiver RSTA The HDLC receiver has written further ...
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Possible Error Conditions during Reception of Frames If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow (RDO) byte in the RSTA byte will be set complete frame is lost, i.e. ...
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N In case of RME the last byte in RFIFO contains 1) * the receive status information RSTA Figure 44 Data Reception Procedures Figure 45 gives an example of an interrupt controlled reception sequence, supposed that a long frame ...
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The host reads the first data block from RFIFO and acknowledges the reception by RMC. Meanwhile the second data block is received and stored in RFIFO. • The second 32 byte block is indicated by RPF which is read ...
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MDS2 MDS1 MDS0 MODE Non Auto/16 Non Auto/8 Transparent Transparent Transparent Description of Symbols: Compared with Registers Stored in FIFO/Registers Figure ...
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The T-SMINT IX indicates to the host that a new data block can be read from the RFIFO by means of a RPF interrupt (see previous chapter). User data is stored in the RFIFO and information about the received ...
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XPR (Transmit Pool Ready) interrupt, indicating that a data block bytes (block size selected via EXMR:XFBS) can be written to the XFIFO. A XPR interrupt is generated either – after a XRES (Transmitter ...
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The XFIFO requests service from the microcontroller by setting a bit in the ISTAH register, which causes an interrupt (XPR, XDU, XMR). The microcontroller can then read the status register STAR (XFW, XDOV), write data in the FIFO and it ...
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Possible Error Conditions during Transmission of Frames If the transmitter sees an empty FIFO, i.e. if the microcontroller does not react quickly enough to a XPR interrupt, a XDU (transmit data underrun) interrupt will be raised. If the HDLC channel ...
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Command XTF Figure 47 Data Transmission Procedure The following description gives an example for the transmission byte frame with a selected block size of 32 byte (EXMR:XFBS=0): • The host writes 32 bytes to the XFIFO, ...
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As soon as the last byte of the first block is transmitted, the T-SMINT interrupt (XFIFO space of first data block is free again) and continues transmitting the second block. • The host writes the remaining 12 bytes of ...
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Transmit Transparent Frame (XTF) 1) The CRC is generated by default EXMR.XCRC is set no CRC is appended Figure 49 Transmit Data Flow 2.6.4 Access to IOM By setting the enable HDLC data bits (EN_D, EN_B1H, EN_B2H) ...
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XMR (transmit message repeat) interrupt and stops transmission. If the microcontroller fails to respond to a XPR interrupt in time and the transmitter runs out of data then it will assert a ...
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CNT VALUE TIMR1 Figure 50 Timer Register 2.6.7 HDLC Controller Interrupts All interrupt sources from the ISTAH register are combined (ORed single HDLC controller interrupt signal hint. Each of ...
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MASK U ST CIC TIN WOV S MOS HDLC INT Figure 51 Interrupt Status Registers of the HDLC Controller 2.6.8 Test Function â The T-SMINT IX provides test and diagnostic functions for the HDLC controller: Digital loop via TLP ...
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Reset Behavior After reset all pointers to the FIFOs are set to “0”, the XPR interrupt is set to “1” but cannot be read by the host masked, i.e. it must be unmasked so it can ...
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Operational Description 3.1 Layer 1 Activation/Deactivation 3.1.1 Generation of 4B3T Signal Elements For control and monitoring purposes of the activation/deactivation progress the following signal elements are defined by TS 102 080 and FTZ 1 TR 220. Table 29 4B3T ...
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Table 29 4B3T Signal Elements (cont’ indicates that the whole link to the TE is synchronous in both directions. On detecting U3 the LT requests the NT by U4H to establish a fully transparent connection. The M-channel on ...
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Table 30 Generation of the 4B3T Signal Elements (cont’d) U4H Table 31 S/T-Interface Signals Signals from INFO 0 No signal. INFO 2 Frame with all bits and D-echo ...
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Complete Activation Initiated by Exchange • â IOM -2 TE S/T-Reference Point INFO INFO 0 INFO 2 AR INFO 3 INFO 4 AI AR8/10 SBCX-X or IPAC-X Figure 53 Activation Initiated by Exchange Note: The LT ...
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Complete Activation Initiated by TE • â IOM -2 TE S/T-Reference Point INFO INFO 0 TIM PU AR8/10 INFO 1 INFO 2 RSY INFO 0 AR INFO 3 INFO 4 AI SBCX-X or IPAC-X Figure 54 ...
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Complete Activation Initiated by NT • IOM â S/T-Reference Point INFO INFO 0 INFO 2 AR INFO 3 INFO 8/10 SBCX-X or IPAC-X Figure 55 Activation Initiated by NT Note: The ...
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Complete Deactivation • IOM â S/T-Reference Point INFO INFO 3 INFO 0 RSY DR INFO SBCX-X or IPAC-X Figure 56 Complete Deactivation Data Sheet NT U-Reference Point ...
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Loop 2 • â IOM -2 TE S/T-Reference Point INFO 4 AI AR8/10 INFO 3 SBCX-X or IPAC-X Figure 57 Loop 2 Note: Closing/resolving loop 2 may provoke the S-transceiver to resynchronize. In this case, the following C/I-codes are ...
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Layer 1 Loopbacks Test loopbacks are specified by the national PTTs in order to facilitate the location of defect systems. Four different loopbacks are defined. The position of each loopback is illustrated in Figure 58. • IOM ® -2 ...
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The S/T interface level detector is enabled, i. level is detected this will be reported by the Resynchronization Indication (RSY) but the loop function is not affected. Depending on the DIS_TX bit in the S_CONF2 register the internal ...
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Complete Loopback When receiving the request for a complete loopback, the U transceiver passes the downstream device, e.g. the S-bus transceiver. This is achieved by issuing the C/I- code AIL in the “Transparent” state or C/I ...
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LOOP.LB1=1 LOOP.LB2=1 LOOP.LBBD= 1 LOOP.U/IOM= Analog Part Digital Part Line Interface Unit DAC Echo Canceller PDM + ADC Filter Timing Recovery U-Transceiver Bandgap, Bias, Refer. Figure 61 Loopbacks Featured by Register LOOP Data Sheet & 1 2B1Q Scrambler A ...
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External Circuitry 3.3.1 Power Supply Blocking Recommendation The following blocking circuitry is suggested. • VDDa_UR VDDa_UX VDDa_SR VDDa_SX VDDD VDDD 1) 100nF VSSD VSSD VSSa_SX VSSa_SR VSSa_UX VSSa_UR 1) These capacitors should be located as near to the pins ...
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AOUT BIN AIN BOUT Figure 63 External Circuitry U-Transceiver with External Hybrid U-Transformer Parameters The following table lists parameters of typical U-transformers. Table 32 U-Transformer Parameters U-Transformer Parameters U-Transformer ratio; Device side : Line side Main inductanc of windings ...
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Resistors of the External Hybrid R3, R4 and 1. 1 Resistors COMP T • Optional use of trafos with non negligible resistance R resistors R depending ...
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S-Transformer Parameters The following Table 33 lists parameters of a typical S-transformer: Table 33 S-Transformer Parameters Transformer Parameters Transformer ratio; Device side : Line side Main inductance of windings on the line side Leakage inductance of windings on the line ...
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SX1 SX2 Figure 64 External Circuitry S-Interface Transmitter Receiver The receiver of the S-transceiver is symmetrical recommended in each receive path preferable to split the resistance into two resistors for each line. This allows to ...
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Oscillator Circuitry Figure 66 illustrates the recommended oscillator circuit. • Figure 66 Crystal Oscillator Table 34 Crystal Parameters Parameter Frequency Frequency calibration tolerance Load capacitance Max. resonance resistance Max. shunt capacitance Oscillator mode External Components and Parasitics The load ...
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Register Description 4.1 Address Space Figure 67 Address Space Data Sheet 7D H U-Transceiver 60 H Monitor Handler 5C H â IOM -2 Handler (CDA, TSDP, CR, STI Interrupt, Global Registers 3C H S-Transceiver 30 H HDLC ...
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Interrupts Special events in the T-SMINT which requests the host to read status information from the T-SMINT â from/to the T-SMINT IX. Since only one INT request output is provided, the cause of an interrupt must be determined by ...
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After the T-SMINT IX has requested an interrupt by setting its INT pin to low, the host must read first the T-SMINT service routine. The INT pin of the T-SMINT are cleared. Therefore possible that the INT ...
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Register Summary r(0) = reserved, implemented as zero HDLC Control Registers, CI Handler Name 7 6 RFIFO XFIFO ISTAH RME RPF MASKH RME RPF STAR XDOV XFW CMDR RMC RRES MODEH MDS2 MDS1 MDS0 EXMR XFBS RFBS TIMR CNT ...
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CIR0 CODR0 CIX0 CODX0 CIR1 CIX1 Data Sheet CIC0 CIC1 TBA2 TBA1 CODR1 CODX1 137 PEF 81902 Register Description S/G BAS TBA0 BAC CICW CI1E CICW CI1E ...
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S-Transceiver Name DIS_ BUS CONF0 TR S_ DIS_ 0 CONF2 TX S_STA RINF S_CMD XINF SQRR MSYN MFEN SQXR 0 MFEN ISTAS 0 x MASKS MODE Data Sheet ...
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Interrupt, General Configuration Name 7 6 ISTA U ST MASK U ST MODE1 MCLK CDS MODE2 LED2 LED1 LEDC SRES 0 0 RES_ CI/TIC Data Sheet CIC TIN WOV S CIC TIN WOV ...
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IOM Handler (Timeslot, Data Port Selection, CDA Data and CDA Control Register) Name 7 6 CDA10 CDA11 CDA20 CDA21 CDA_ DPS 0 TSDP10 CDA_ DPS 0 TSDP11 CDA_ DPS 0 TSDP20 CDA_ DPS 0 TSDP21 S_ DPS 0 TSDP_ B1 ...
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IOM Handler (Control Registers, Synchronous Transfer Interrupt Control) Name 7 6 S_CR 1 CI_CS HCI_CR DPS_ EN_ CI1 CI1 MON_ DPS EN_ CR MON SDS1_ ENS_ ENS_ CR TSS TSS+1 SDS2_ ENS_ ENS_ CR TSS TSS+1 IOM_CR SPU 0 MCDA ...
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MONITOR Handler Name 7 6 MOR MOX MOSR MDR MER MOCR MRE MRC MSTA 0 0 MCONF 0 0 Data Sheet MONITOR Receive Data MONITOR Transmit Data MDA MAB 0 0 MIE MXC ...
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U-Transceiver Name 7 6 OPMODE 0 UCI UCIR 0 0 UCIW 0 0 LOOP 0 0 RDS ISTAU 0 CI MASKU 1 CI FW_ VERSION Note: Registers, which are denoted as ‘reserved‘, may not be accessed by the µC, neither ...
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Table 35 Reset of U-Transceiver Functions During Deactivation or with C/I- Code RESET Register Affected Bits/ Comment LOOP only the bits LBBD, LB2 and LB1 are reset 4.3.2 Mode Register Evaluation Timing Table 36 lists registers, which are evaluated ...
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Detailed HDLC Control and C/I Registers 4.4.1 RFIFO - Receive FIFO RFIFO 7 The RFIFO contains bytes of received data. After an ISTAH.RPF interrupt, a complete data block is available. The block size can be 4, ...
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Note: The reset value cannot be read right after reset as all interrupts are masked, i.e. the XPR interrupt remains internally stored and can only be read as soon as the corresponding mask bit is set to “0” ...
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A data block the defined block size (EXMR.XFBS) can be written to the XFIFO. A XPR interrupt will be generated in the following cases: • after a XTF or XME command as soon as the ...
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RME RPF Each interrupt source in the ISTAH register can be selectively masked by setting the corresponding bit in MASKH to ‘1’. Masked interrupt status bits are not indicated when ISTAH is read. Instead, they remain internally stored ...
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The HDLC receiver is active when RACI = ‘1’. This bit may be polled. The RACI bit is set active after a begin flag has been received and is reset after receiving an abort sequence. XACI Transmitter Active ...
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After having written bytes (EXMR.XFBS) in the XFIFO, the microcontroller initiates the transmission of a transparent frame by setting this bit to ‘1’. The opening flag is automatically added to the message by ...
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MDS2-0 Mode Select Determines the message transfer mode of the HDLC controller, as follows : MDS2-0 Mode Reserved Reserved Non-Auto mode Non-Auto mode/ Extended transparent ...
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DIM2-0 Digital Interface Modes These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit enables/disables the stop/go bit (S/G) evaluation. The DIM1 bit enables/disables the TIC bus access. The effect of the individual DIM bits ...
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SRA Store Receive Address 0 = Receive Address is not stored in the RFIFO 1 = Receive Address is stored in the RFIFO XCRC Transmit CRC 0 = CRC is transmitted 1 = CRC is not transmitted RCRC Receive CRC ...
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CNT CNT together with VALUE determines the time period T after which a TIN interrupt (ISTA) will be generated in the normal case: CNT=0... CNT x 2.048 sec + T1 with T1 = (VALUE+1) x 0.064 sec CNT=7: ...
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SAP2 - SAPI2 Register SAP2 Value after reset SAPI2 SAPI2 value Value of the programmable high address byte. In ISDN LADP protocol (D- channel) this is the Service Access Point Identifier (SAPI) and for B-channel applications ...
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RBCH - Receive Frame Byte Count High for D-Channel RBCH Value after reset r(0) r(0) OV Overflow 0 = Message shorter than ( Message longer than (2 RBC8-11 Receive Byte Count Four most ...
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TEI1 Terminal Endpoint Identifier In all message transfer modes except for transparent modes 0, 1 and extended transparent mode, TEI1 is used by the T-SMINT recognition. In the case of a two-byte address field, it contains the value of the ...
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VFR RDO VFR Valid Frame Determines whether a valid frame has been received. A frame is invalid when there is not a multiple of 8 bits between flag and frame end (flag, abort The frame is invalid ...
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These bits are only relevant in modes with address comparison. The result of the address comparison is given by SA1-0 and TA, as follows: MDS2-0 010 (Non-Auto/8 Mode) 011 (Non-Auto/16 Mode) 111 (Transparent Mode 1) 101 (Transparent Mode 2) Note: ...
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TLP Test Loop 0 = inactive 1 = The TX path of the HDLC controller is internally connected to its RX path. Data coming from the IOM-2 will not be forwarded to the HDLC controller. Setting of TLP is only ...
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S/G Stop/Go Bit Monitoring Indicates the availability of the upstream D-channel Stop BAS Bus Access Status Indicates the state of the TIC-bus the T-SMINT 1 = another device occupies the D- and C/I-channel ...
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The T-SMINT channel even if no D-channel frame has to be transmitted. It should be reset when the access has been completed to grant a similar access to other devices transmitting in that IOM-channel. Note: ...
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CODX1 C/I1-Code Transmit Bits 5-0 of C/I-channel 1 CICW C/I-Channel Width bit C/I1 channel width bit C/I1 channel width The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected, ...
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All S-transceiver functions are disabled and powered down (analog and digital parts). BUS Point-to-Point / Bus Selection 0 = Adaptive Timing (Point-to-Point, extended passive bus Fixed Timing (Short passive bus), directly derived from transmit clock. EN_ICV ...
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DIS_TX 0 DIS_TX Disable Line Driver 0 = Transmitter is enabled 1 = Transmitter is disabled 4.5.3 S_STA - S-Transceiver Status Register S_ STA Value after reset RINF Important: This register is used only if the ...
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LD Level Detection receive signal has been detected on the line Any receive signal has been detected on the line. 4.5.4 S_CMD - S-Transceiver Command Register S_ CMD Value after reset XINF ...
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The transceiver is set to power down mode LP_A Loop Analog The setting of this bit corresponds to the C/I command ARL Analog loop is open 1 = Analog loop is closed internally or externally according ...
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MFEN MFEN Multiframe Enable Used to enable or disable the multiframe structure S/T multiframe is disabled 1 = S/T multiframe is enabled SQX1-4 Transmitted S/Q Bits Transmitted S bits in frames and 16 ...
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RIC Receiver INFO Change 0 = inactive 1 = RIC is activated if one of the S_STA bits RINF or ICV has changed. SQC S/Q-Channel Change 0 = inactive change in the received 4-bit Q-channel has been ...
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The transceiver interrupts LD, RIC, SQC and SQW are enabled 1 = The transceiver interrupts LD, RIC, SQC and SQW are masked 4.5.9 S_MODE - S-Transceiver Mode S_ MODE Value after reset DCH_ ...
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Interrupt and General Configuration Registers 4.6.1 ISTA - Interrupt Status Register ISTA Value after reset U-Transceiver Interrupt 0 = inactive interrupt was generated by the U-transceiver. Read the ISTAU register. ...
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Signals the expiration of the watchdog timer, which means that the microcontroller has failed to set the watchdog timer control bits WTC1 and WTC2 (MODE1 register) in the correct manner. A reset out pulse on pin RSTO has ...
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Each interrupt source in the ISTA register can be selectively masked by setting the corresponding bit in MASK to ‘1’. Masked interrupt status bits are not indicated when ISTA is read. Instead, they remain internally stored and pending, until the ...
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If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset out pulse on pin RSTO is generated. The watchdog timer runs only when the internal IOM ...
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1 flashing 1 Low LEDC LED Control Enable 0 = LED is controlled by the state machines as defined LED ...
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Distinction of different firmware versions is also possible by reading register (7D) U-transceiver (see Chapter 4.9.8). 4.6.6 SRES - Software Reset Register SRES Value after reset RES_xx Reset_xx 0 = Deactivates the reset of ...
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CDA20 FF H CDA21 FF H 4.7.2 XXX_TSDPxy - Time Slot and Data Port Selection for CHxy XXX_TSDPxy 7 DPS 0 Register Value after Reset CDA_TSDP10 00 H CDA_TSDP11 01 H CDA_TSDP20 80 H CDA_TSDP21 81 H reserved S_TSDP_B1 84 ...
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TSS Timeslot Selection Selects one of the 12 timeslots from 0...11 on the IOM data channels. 4.7.3 CDAx_CR - Control Register Controller Data Access CH1x CDAx_CR Register Value after Reset Register Address CDA1_CR 00 H CDA2_CR 00 ...
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SWAP Swap Inputs 0 = The time slot and data port for the input of the CDAxy register is defined by its own TSDPxy register. The data port for the CDAxy input is vice versa to the output setting for ...
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The corresponding data path to the transceiver is enabled. EN_B1R Enable Transceiver B1 Receive Data (transmitter receives from IOM The corresponding data path to the transceiver is disabled 1 = The corresponding data path to the ...
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EN_CI1 Enable CI1 Handler 0 = CI1 data access is disabled 1 = CI1 data access is enabled Note: The timeslot for the C/I1 handler cannot be programmed but is fixed to IOM channel 1. EN_D Enable D-timeslot for HDLC ...
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The HDLC data is read and output on IOM-channel Not defined 1) If the TIC-bus is enabled, then an HDLC access in IOM-channel 2 is possible only to the B channels. 4.7.6 MON_CR - Control ...
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ENS_ ENS_ TSS TSS+1 This register is used to select position and length of the strobe signal 1. The length can be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot (ENS_TSS+3). ENS_ Enable Serial Data ...
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ENS_ ENS_ TSS TSS+1 This register is used to select position and length of the strobe signal 2. The length can be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot (ENS_TSS+3). ENS_ Enable Serial Data ...
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SPU 0 SPU Software Power The DU line is normally used for transmitting data Setting this bit to ‘1’ will pull the DU line to low. This will enforce the T-SMINT clocking. TIC_DIS TIC ...
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MCDA - Monitoring CDA Bits MCDA Value after reset MCDA21 Bit7 Bit6 MCDAxy Monitoring CDAxy Bits Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register. This can be used for ...