MCZ33780EG Freescale, MCZ33780EG Datasheet

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... GND Figure 1. 33780 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. Device MC33780EG/R2 MCZ33780EG/R2 +5.0 V +25 V 33780 VCC VSUP SCLK Twisted Pair ...

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... Interrupt CS Generator INT RST 33780 2 INTERNAL BLOCK DIAGRAM VCC VSUP DSIF DSIS DSIR DSIF DSIS DSIR SPI, T LIM Figure 2. 33780 Internal Block Diagram D0H DBUS Driver/Receiver D0L D1H DBUS Driver/Receiver D1L GND GND GND Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... VCC Input 10 GND Ground 11 D1L Output Driver 12 D1H Output Driver 13 VSUP Output 14 D0H Output Driver 15 D0L Output Driver 16 GND Ground Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS 1 RST INT 3 14 MOSI MISO 6 11 CLK 7 10 GND 8 9 Figure 3. 33780 Pin Connections ...

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... Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. ...

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... InH ≤ 1.0 mA, -1.0 mA ≤ InL ≤ 12.5 mA Notes 4 Not measured in production. 5 InH = bus current at DnH, InL = bus current at DnL Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 5.25 V, 9.0 V ≤ V ≤ 25 V,- 40°C ≤ SUP Symbol ) CC I VSUP I VCC HYST ...

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... Typ Max Unit V 1.5 1.825 SUP SUP 2 + 1.0 0.3 – – -200 – – mA – -100 – 400 mA – -30 – 100 mA – -30 – 100 mA -0.18 1.0 0.25 1.0 mA -0.4 1.0 0.08 1.0 6.0 7.0 mA Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Fall Time (70 30 SCLK, MISO Notes 8 Not measured in production. 9 SPI signal timing from the production test equipment is programmed to ensure compliance. Analog Integrated Circuit Device Data Freescale Semiconductor DYNAMIC ELECTRICAL CHARACTERISTICS ≤ 5.25 V, 9.0 V ≤ V ≤ 40°C ≤ SUP Symbol Min tCLKHI 75 tCLKLO 75 ...

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... BIT 1 – 4 BIT BIT µs – 6.0 6.56 0.25 0.8 1.3 0.25 0.8 1.3 – 0.8 1.3 µs 2.0 – 20 µs -0.8 2 -0.6 2 -0.4 BIT BIT BIT µs -0.8 1 -0.6 1 -0.4 BIT BIT BIT Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Frame Jitter (Max) ( CEN CEN CEN DEV On DEV Off Notes 17 Delays are measured in test mode to determine the delay for analog signal path. Analog Integrated Circuit Device Data Freescale Semiconductor ≤ 5.25 V, 9.0 V ≤ SUP Symbol (17) t DRH t DRL t CC DRH ...

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... DVLD1 V DnD SUP 6.5 V 5.5 V 4.5 V 3.9 V 2 OUT 6 DRH 5.0 V DSIR 0 V 33780 10 TIMING DIAGRAMS t t CYC CYC Logic 1 Logic 0 t DVLD3 t DVLD2 t DRL Figure 4. DBUS Timing Characteristics t CYC t DVLD4 t SLEW(FRAME) t SLEW(SIGNAL Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... DnL 0 V DnH V SUP Overvoltage Threshold V + 2.25 V mid V + 0.75 V mid V (Clamped) mid V - 0.75 V mid V - 2.25 V mid DnL 0 V Analog Integrated Circuit Device Data Freescale Semiconductor Figure 5. DBUS Normal Bus Waveforms Figure 6. DBUS Overvoltage Bus Waveforms ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS 33780 11 ...

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... MISO MSB Don’t care , DBUS (DnH-DnL) INT CS SCLK MOSI 33780 12 t CYC Figure 7. SPI Interface Timing t INTON Figure 8. INT and Bus Start Timing LAG LSB LSB t DIS V OH LSB DBUSSTART t INTOFF Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... MASTER OUT/SLAVE IN (MOSI) This is the SPI data input to the device. This data is sampled on the positive (rising) edge of SCLK. Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTIONS INTRODUCTION amount of change between the two bus wires, the capacitance to ground only conducts half as much current as it would if connected directly across the bus ...

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... FIFO becomes empty. Both of these events are checked at the end of an SPI word (either with edge of SCLK of a new data byte in an SPI burst). Register and Bit INT to pull down the output. Interrupts CS rising or with the rising Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Analog Integrated Circuit Device Data Freescale Semiconductor The DBUS transmit protocol uses a return to 1 type data with a duty cycle determined by the logic state. The protocol requires Cyclical Redundancy Check (CRC) generation and validation. Comp. Signal Signal Figure 10. Driver/Receiver Block Diagram The DBUS driver block diagram is shown in circuit uses independent drivers for the Idle and Signal states ...

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... S for the interference to be filtered. Figure 11 BUS Figure 11. Receive Filter / 3.0 µA/mA (the amplifier saturates with 1 BUS TH BUS and the duration of BUS TH Analog Integrated Circuit Device Data Freescale Semiconductor DnH DSIR ) ...

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... Because they are evenly spaced by a time difference and not by a frequency difference (the reciprocal of time), all frequency domain parameters of the SS block are expressed in units of time. Analog Integrated Circuit Device Data Freescale Semiconductor PLL Logic SSUD Center Frequency DAC ...

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... The Spreader Logic is synchronized to only change the value of the digital word to the Spreader DAC at the beginning of a DBUS bit. When spreading is enabled, these changes will occur once per DBUS bit-time. Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Data is transmitted on DSIS and received on DSIR pins simultaneously. Receive data is the captured level on the DSIR pin at the end of each Analog Integrated Circuit Device Data Freescale Semiconductor LOGIC COMMANDS AND REGISTERS pointer to the desired register. Bits 5 and 6 are unused. See Figure 13 ...

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... CRC algorithm for the DBUS standard 4-bit CRC with its initial value of 1010. A seed value is chosen so kHz that a zero data value will generate a CRC value of 1010. A block diagram of the default CRC calculation is shown in 121.2 Figure 17. 136.1 150.1 158.9 Figure VHDL Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... Bits three to zero of the data and the CRC bits are lost. Data bits seven to four of the 16-bit response message look like the CRC bits of an 8-bit response and almost certainly would not be correct. Because the response Analog Integrated Circuit Device Data Freescale Semiconductor Figure 16. CRC Algorithm ...

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... CH0 Enable CH1 Enable RX FIFO RX Buffer RX Buffer RX Buffer RX Buffer CH1 TX FIFO TX Buffer TX Buffer TX Buffer TX Buffer output pin. The main INT output can only drive the INT is used to pull this pin high. This is done so CC Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... CH0/CH1 OUTPUTS These signals control the physical layer drivers and receive data from the physical layer receivers. The physical Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS layer will convert the 5.0 V low power logic signals to the higher voltage ( ...

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... These conditions cause an asynchronous entry into this state. The exit to the next state, WAIT_SIG_DLY_0, needs to be synchronous. STATE TRANSITIONS OCCUR ON POS EDGE OF XXX CLK goes high (or the CS STATE TRANSITIONS OCCUR ON POS EDGE OF SCLK SPI_BIT_PTR = SPI_BIT_PTR-1; SPI_BIT_PTR = SPI_BIT_PTR-1; Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... DBUS_BIT_PTR = 8 to 15, OR 23; DSIS = 0; XFER_DBUS_BIT_0 DBUS_X_POP X_FIFO_POP = 0; Analog Integrated Circuit Device Data Freescale Semiconductor out even while the DBUS_R_PUSH and DBUS_X_POP states are being processed. Figure 22 describes the operation of the transmit FIFO. This FIFO is four levels deep, including the stage which is written into by the SPI and the stage which provides the data for the current DBUS serial transfer ...

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... Since it is not possible to introduce another DBUS serial character without reading (pop) the receive FIFO not possible to overflow the receive FIFO. STATE TRANSISTIONS OCCUR ON NEG EDGES OF X_FIFO_PUSH AND X_FIFO_POP X_FIFO_PUSH & X_PUSHPTR != X_POP_PTR-1 X_PUSH_PTR = X_PUSH_PTR+1; Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... D1OFFSETL DBUS 0 spread spectrum up/down counter 10100 D0SSUD DBUS 1 spread spectrum up/down counter 10101 D1SSUD Analog Integrated Circuit Device Data Freescale Semiconductor RX_IDLE R_FIFO_PUSH/ R_PUSH_PTR = R_PUSH_PTR+1; R_FIFO_EMPTY = FALSE; R_FIFO_PUSH & R_PUSHPTR != R_POP_PTR-1/ RX_NOT_EMPTY R_FIFO_PUSH & R_PUSH_PTR = R_POP_PTR-1/ R_FIFO_POP/ R_PUSH_PTR = R_PUSH_PTR+1; ...

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... Unused bit positions are don’t care values Bit 13 Bit 12 Bit Figure 25. DnH Data Register Bit Assignments DnL Tx (Write-Only) RFNEn RIEn Interrupt Request Figure 25. When a short Bit 10 Bit 9 Bit Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... FIFO without checking the flags between writes. will be asserted on the transmit FIFO INT Analog Integrated Circuit Device Data Freescale Semiconductor low byte of a 16-bit return on the DBUS. Writing to this register initiates a DBUS transaction. The bit assignments are shown in . ...

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... This will result in an all 0 response, which will cause a CRC error Figure 29. DEN Register Bits TIE pin will be low to request an INT Table 10. The clock divider is DIV[1: EN1 EN0 Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... A write to the register will abort any current activity on the bus. Any bit changes will take place on the next DBUS Analog Integrated Circuit Device Data Freescale Semiconductor The ENn bits are cleared and the channel disabled if a thermal shutdown occurs necessary to write the ENn bit to turn it back on ...

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... XOR tap position on the PRBS. The following encoding of this field. Table 11. PRBS Bit Encoding PRBS[1: Figure 33 DEV1 DEV0 0 0 Table 11 describes the bit PRBS Reg XOR Input A XOR Input B Length Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... PLL.A write to the register will be ignored. The 6-bit SSUD value will be latched Analog Integrated Circuit Device Data Freescale Semiconductor The mode with deviation disabled may be used to achieve fine control of the bit rate without frequency spreading. DnOFFSETH and DnOFFSETL REGISTERS These read/write registers control the spread spectrum PLL offset value ...

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... When a DBUS channel is disabled, the 33780 device forces its bus output to tri-state. The transmit and receive FIFO pointers are reset and the FIFO locations are forced to zero. Any DBUS transfer that was in progress is stopped. Analog Integrated Circuit Device Data Freescale Semiconductor ...

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... For the most current package revision, visit Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS www.freescale.com and perform a keyword search using the “98A” listed below. PACKAGING PACKAGE DIMENSIONS 33780 35 ...

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... Changed Soldering Reflow Temperature from 250 to 260 Maximum 5/2006 • Changed DnSSUD Registers on page 33. 3.0 • Added MCZ33780EG/R2 11/2006 4.0 • Updated with the current Freescale format and style • Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...