FAGD16556ECLBA Intel, FAGD16556ECLBA Datasheet - Page 13

• Manufacturer Part Number: FAGD16556ECLBA
• Manufacturer: Intel

Specifications of FAGD16556ECLBA

• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

Table 1: Valid combinations of VCXO centre frequency and clock generator divider settings for the transponder system shown on
Note on reading the table.
For the explanation below please refer to
Standard bit rates is understood as STM-1 / OC3, STM-4 / OC12, STM-16 / OC48 and Gigabit Ethernet (1.25 Gbit/s)
Reading the table is illustrated by the following example. Consider the wrap fraction 15/14. In this case the system must be
equipped with two VCXOs. The first VCXO centre frequency equals 44,434286 MHz (SDH/SONET traffic) and the second VCXO
centre frequency equals 44,642857 MHz (GE traffic). When the system receives and transmits data at standard bit rates the system
settings is read from the row “Standard bit rates with programmable 15/14 overhead”. If the system receives data at rates increased
by 15/14 and transmits data at standard bit rates the system settings is read from the row “15/14 on receiving side”. If the system
receives standard bit rates and transmits data at a rate increased by 15/14 the system settings is read from the row 15/14 on trans-
mitting side. Finally, if the system receives and transmits at data rates increased by 15/14 the system settings are read from the row
“15/14 on transmitting side and receiving side”.
Figure 22.Definition of receiving and transmitting side with respect to Table 1.
Data Sheet Rev.: 23
Standard Bit Rate
STM-1 / OC 3
STM-4 / OC 12
STM-16 / OC 48
GE
STM-1 / OC 3
STM-4 / OC 12
STM-16 / OC 48
GE
STM-1 / OC 3
STM-4 / OC 12
STM-16 / OC 48
GE
Figure 1.
STM-1 / OC3
STM-4 / OC12
STM-16 / OC48
Gigabit
Ethernet
“Wrap” fraction
32/31 on receiving
32/31 on transmit-
32/31 on transmit-
Receiving Side
ting side and re-
Times:
1,
15/14,
16/15,
32/31
ceiving side
ting side
side
DeMUX 1:16
GD16556
CDR &
Figure
VCXO Centre
Frequency
40,134194
40,134194
40,134194
40,322581
40,134194
40,134194
40,134194
40,322581
40,134194
40,134194
40,134194
40,322581
16
Clock
22.
[MHz]
GD16556/GD16557*
System
Clock
Clock
ASIC
GD16556 select pin settings
RSEL1/2
“10"
"01"
"11"
"00"
“10"
"01"
"11"
"00"
“10"
"01"
"11"
"00"
16
Clock
VCXO
MSEL1/2
"11"
"11"
"11"
"11"
"10"
"10"
"10"
"10"
"11"
"11"
"11"
"11"
Cleaner &
MUX 16:1
GD16557
Jitter
Transmitting Side
Times:
1,
15/14,
16/15,
32/31
GD16557 select pin settings
RSEL1/2
“10"
"01"
"11"
"00"
“10"
"01"
"11"
"00"
“10"
"01"
"11"
"00"
STM-1 / OC3
STM-4 / OC12
STM-16 / OC48
Gigabit
Ethernet
Page 13 of 28
MSEL1/2
"10"
"10"
"10"
"10"
"11"
"11"
"11"
"11"
"11"
"11"
"11"
"11"