SLXT970AQC.B11-831643 Cortina Systems Inc, SLXT970AQC.B11-831643 Datasheet - Page 14

• Manufacturer Part Number: SLXT970AQC.B11-831643
• Manufacturer: Cortina Systems Inc

Specifications of SLXT970AQC.B11-831643

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 5V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

Intel
14
1. Pin numbers apply to all package types.
2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.
3. FDE, CFG0, and CFG1 are affected by the MDDIS input pin. When MDDIS = 0, these inputs determine only the initial state
Pin#
of the function they control. When MDDIS = 1, these inputs provide continuous hardware control over their corresponding
functions.
8
7
6
5
4
Table 7.
®
1
LXT970A Dual-Speed Fast Ethernet Transceiver
Pin Name
MF0
MF1
MF2
MF3
MF4
Hardware Control Interface Signal Descriptions (Sheet 1 of 2)
I/O
I
2
Multi-Function (MF). Five dual-function configuration inputs. Each pin accepts one of four
input voltage levels (V
A simple resistor divider network, as shown in
Mid-level (V
with the LXT970A Transceiver standard power supply and do not require a voltage divider.
One voltage divider may be used to drive the MF pins in designs using multiple
LXT970A Transceivers.
Each MF pin internally drives two different configuration functions. The first function
determines the 5-bit address that the LXT970A Transceiver responds to on the MDIO line.
The second function determines a particular operational mode of the LXT970A Transceiver.
Each MF pin also determines the state of a particular bit in the MII registers. The MDDIS input
determines if this effect occurs only at initialization (MDDIS = 0) or continuously (MDDIS = 1).
The relationship between the input levels and the two configuration functions are shown in
Table 8 on page 16
The operating functions of MF4, CFGO, and CFG1 change depending on the state of MF0
(Auto-Negotiation enabled or disabled). The functions of MF4, CFG1 and FDE are
interrelated.
The functions of the five MF inputs are as follows:
MF0
MF1
MF2
MF3
MF4
Pin
MII Address
MF
2 and V
0
1
2
3
4
and
MF
MF
Table 9 on page
1 = 5V, V
3) settings. V
MII Bit
19.13
0.12
19.4
19.3
19.2
4.7
4.8
MF
Signal Description
2 = 3.5V, V
Auto-Negotiation
Repeater Mode (Disabling DTE Mode)
5B Symbol Mode (Disabling 4B Nibble Mode)
Scrambler Operation (Disabling Scrambler)
Auto-Negotiation Enabled - Advertise 100 Mbps
Auto-Negotiation Disabled - Selects TX/FX
MF
1 and V
17.
Figure 20 on page
MF
MF
3 = 1.5V, V
4 (default) settings, can be established
Operating Function
3
MF
4 = 0V).
45, is required to establish
Datasheet