SLXT970AQC.B11-831643 Cortina Systems Inc, SLXT970AQC.B11-831643 Datasheet - Page 25

• Manufacturer Part Number: SLXT970AQC.B11-831643
• Manufacturer: Cortina Systems Inc

Specifications of SLXT970AQC.B11-831643

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 5V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Figure 8. MDIO Interrupt Signaling
Figure 9. Management Interface - Read Frame Structure
(Read)
MDIO
MDC
Idle
Preamble
32 "1"s
registers. The physical interface consists of a data line (MDIO) and clock line (MDC), a control
line (MDDIS) and an optional interrupt line (MDINT). The LXT970A Transceiver can signal an
interrupt using the MDIO signal as shown in
this function. If bit 17.1 = 1, pin 2 (FDS/MDINT) will be used as an MDINT pin.
The protocol allows one controller to communicate with multiple LXT970A Transceiver devices.
The MF pins control one bit each of the 5-bit address setting. Each LXT970A Transceiver is
assigned an MII address between 0 and 31. Details of the MF inputs are shown in
page
operations are shown in
MDDIS input pin. When MDDIS is High, the MDIO operates as a read-only interface. When
MDDIS is Low, read and write are enabled.
The LXT970A Transceiver supports twelve 16-bit MDIO registers. Registers 0-6 are required and
their functions are specified by the IEEE 802.3 specification. Additional registers are included for
expanded functionality. The MDIO Register set for the LXT970A Transceiver is described in
45
is the register number (0-6 or 16-20) and Y is the bit number (0-15).
MII Management Interrupt
The MDINT/FDS pin functions as a management data interrupt on the MII when 17.1 = 1. An
active Low on this pin indicates a status change on the LXT970A Transceiver. The interrupt is
activated when changes are made to the following conditions:
This interrupt is cleared by sequentially reading Register 1 and Register 18.
•
•
Interrupt
through
MDIO
MDC
Link Status
Duplex Status
0
14. Timing for the MDIO Interface is shown in
SFD
1
Table
Z
Around
Turn
1
Op Code
56. Specific bits in the registers are referenced using an “X.Y” notation, where X
0
0
Write
Figure 9
A4
MDIO FRAME
PHY Address
Sourced by
Read Data
LXT970A
A3
and
Intel
A0
Figure
®
R4
LXT970A Dual-Speed Fast Ethernet Transceiver
Register Address
10. Operation of this interface is controlled by the
Figure
R3
R0
8. The user can also assign a separate pin for
Table 42 on page
INT
Z
Around
Turn
0
Idle
D15
D15
D14
Data
Read
61. Read and write
D14
D1
D1
D0
Table 7 on
Idle
Table
25