SLXT970AQC.B11-831643 Cortina Systems Inc, SLXT970AQC.B11-831643 Datasheet - Page 33

• Manufacturer Part Number: SLXT970AQC.B11-831643
• Manufacturer: Cortina Systems Inc

Specifications of SLXT970AQC.B11-831643

• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 5V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

2.6.2
Datasheet
Figure 13. 100BASE-TX Frame Structure
Figure 14. 100BASE-TX Data Flow
Standard Data Flow
Symbol (5B) Mode Data Flow
Scrambler Bypass Data Flow
D0
D1
D2
D3
S0
S1
S2
S3
S4
S0
S1
S2
S3
S4
Replaced by
/J/K/ code-groups
Start of Stream
Delimiter (SSD)
P0
In some applications it may be desirable to bypass the 4B/5B encoder/decoder circuit, and operate
the MII as a 5-bit symbol mode interface. The LXT970A Transceiver provides additional lines in
both the receive and transmit channels (RXD4 & TXD4) to accommodate MACs that accept 5-bit
symbols.
100BASE-X Network Operations
During 100BASE-X operation, the LXT970A Transceiver transmits and receives 5-bit symbols
across the network link.
is not actively transmitting data, the LXT970A Transceiver sends out Idle symbols on the line.
In 100TX mode, the LXT970A Transceiver scrambles the data using a polynomial key, and
transmits it to the network using MLT-3 line code. The MLT-3 signals received from the network
are descrambled and decoded by the LXT970A Transceiver, and sent across the MII to the MAC.
In 100FX mode, the LXT970A Transceiver transmits and receives NRZI signals across the pseudo-
ECL interface. An external 100FX transceiver module is required to complete the fiber
connection. To enable 100FX operation, auto-negotiation must be disabled and FX selected.
Parallel
Parallel
Parallel
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Serial
64-Bit Preamble
to
to
to
to
to
to
P1
(8 Octets)
P6
Delimiter (SFD)
D0
Start of Frame
SFD
D1
DA
D2
Address (6 Octets each)
Destination and Source
D3
DA
Figure 13
SA
4B/5B
SA
shows the structure of a standard frame packet. When the MAC
Intel
S0
S0
Packet Length
L1
(2 Octets)
®
S1
S1
LXT970A Dual-Speed Fast Ethernet Transceiver
L2
S2
S2
(Pad to minimum packet size)
D0
S3
S3
Data Field
S4
S4
D1
Dn
Scramble
Scramble
Scramble
Scramble
De-
De-
Frame Check Field
(4 Octets)
CRC
End of Stream Delimiter (ESD)
MLT3
MLT3
MLT3
/T/R/ code-groups
Replaced by
InterFrame Gap / Idle Code
I0
pattern: 0, +1, 0, -1, 0, +1...
pattern: 0, +1, 0, -1, 0, +1...
pattern: 0, +1, 0, -1, 0, +1...
All transitions must follow
All transitions must follow
All transitions must follow
0
0
0
(> 12 Octets)
No Transition = 0.
No Transition = 0.
No Transition = 0.
Transition = 1.
Transition = 1.
Transition = 1.
+1
+1
+1
IFG
0
0
0
-1
-1
-1
0
0
0
33