S2068TB Applied Micro Circuits Corporation, S2068TB Datasheet

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S2068TB

Manufacturer Part Number
S2068TB
Description
Manufacturer
Applied Micro Circuits Corporation
Datasheet

Specifications of S2068TB

Number Of Receivers
2
Protocols Supported
IEEE 802.3z
Operating Supply Voltage (typ)
3.3V
Operating Temperature Classification
Commercial
Operating Supply Voltage (max)
3.47V
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Lead Free Status / RoHS Status
Not Compliant

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FEATURES
APPLICATIONS
Figure 1. Typical Dual Gigabit Ethernet Application
DEVICE
SPECIFICATION
DUAL GIGABIT ETHERNET TRANSCEIVER
DUAL GIGABIT ETHERNET TRANSCEIVER
October 13, 2000 / Revision D
• Functionally compliant with IEEE 802.3z Gigabit
• 1250 MHz (Gigabit Ethernet) operating rate
• Dual Transmitter incorporating phase-locked
• Dual Receiver PLL provides clock and data
• Internally series terminated TTL outputs
• Low-jitter serial PECL interface
• Local Loopback
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 1.37W power dissipation
• Compact 21mm x 21mm 156 TBGA package
• Ethernet Backbones
• Multi-port Gigabit Ethernet Cards
• Switched networks
• Data broadcast environments
High-speed data communications
Ethernet Applications
– Half rate operation
loop (PLL) clock synthesis from low speed
reference
recovery
INTERFACE
ETHERNET
GIGABIT
DUAL
GE INTERFACE
S2068
GENERAL DESCRIPTION
The S2068 dual transmitter and receiver chip is de-
signed to provide two channels of high-speed serial
data transmission over fiber optic or copper interfaces
conforming to the requirements of the IEEE 802.3z
Gigabit Ethernet specification. The chip runs at
1250.0 Mbps serial data rate with an associated
10-bit parallel data word. The chip provides two sepa-
rate receive PLLs which can be operated asynchro-
nously at slightly different frequencies.
Each bi-directional channel provides parallel to serial
and serial-to-parallel conversion, clock generation
and recovery, and framing. The on-chip transmit PLL
synthesizes the high-speed clock from a low-speed
reference. The on-chip dual receive PLL is used for
clock recovery and data re-timing on the two inde-
pendent data inputs. The transmitter and receiver
each support differential PECL-compatible I/O for
copper or fiber optic component interfaces and pro-
vide excellent signal integrity. Local loopback mode
allows for system diagnostics. The chip requires a
3.3V power supply and dissipates 1.37 watts.
Figure 1 shows the use of the S2062 and S2068 in a
Gigabit Ethernet application. Figure 2 summarizes
the input/output signals of the device. Figures 3 and
4 show the transmit and receive block diagrams, re-
spectively.
(ASIC)
(ASIC)
MAC
MAC
SERIAL BP DRIVER
S2062
TO SERIAL
BACKPLANE
S2068
S2068
®
1

Related parts for S2068TB

S2068TB Summary of contents

Page 1

DEVICE SPECIFICATION DUAL GIGABIT ETHERNET TRANSCEIVER DUAL GIGABIT ETHERNET TRANSCEIVER FEATURES • Functionally compliant with IEEE 802.3z Gigabit Ethernet Applications • 1250 MHz (Gigabit Ethernet) operating rate – Half rate operation • Dual Transmitter incorporating phase-locked loop (PLL) clock synthesis ...

Page 2

S2068 Figure 2. S2068 Input/Output Diagram RESET RATE REFCLK CLKSEL TMODE TCLKO DINA[0:9] 10 TBCA DINB[0:9] 10 TBCB COM_DETA DOUTA[0:9] 10 RBC1/0A COM_DETB DOUTB[0:9] 10 RBC1/0B TESTMODE TESTMODE1 CMODE 2 DUAL GIGABIT ETHERNET TRANSCEIVER LPEN October 13, 2000 / Revision ...

Page 3

DUAL GIGABIT ETHERNET TRANSCEIVER Figure 3. Transmitter Block Diagram RATE REFCLK CLKSEL TMODE 10 DINA[0:9] FIFO (input TBCA 10 DINB[0:9] FIFO (input TBCB October 13, 2000 / Revision D DIN PLL 10x/20x 10 Shift Reg 10 ...

Page 4

S2068 Figure 4. Receiver Block Diagram CMODE RATE REFCLK 2 RBC1/0A COM_DETA FIFO (output DOUTA[0:9] 2 RBC1/0B COM_DETB FIFO (output) 10 DOUTB[0:9] 4 DUAL GIGABIT ETHERNET TRANSCEIVER TMODE DOUT CRU 10 Serial- Parallel DOUT CRU 10 Serial- Parallel ...

Page 5

DUAL GIGABIT ETHERNET TRANSCEIVER TRANSMITTER DESCRIPTION The transmitter section of the S2068 contains a single PLL which is used to generate the serial rate transmit clock for all transmitters. Transmitter functionalities shown schematically in Figure 3. Two channels are provided ...

Page 6

S2068 The TBC must be frequency locked to REFCLK, but may have an arbitrary but fixed phase relationship. Adjustment of internal timing of the S2068 is per- formed during reset. Once synchronized, the S2068 can tolerate up to 3ns of ...

Page 7

DUAL GIGABIT ETHERNET TRANSCEIVER The frequency of the reference clock must be either 1/10 the serial data rate, CLKSEL = 0, or 1/20 the serial data rate, CLKSEL = 1. Note that in both cases, the frequency of the parallel ...

Page 8

S2068 Serial-to-Parallel Conversion Once bit synchronization has been attained by the S2068 CRU, the S2068 must synchronize to the 10 bit word boundary. Word synchronization in the S2068 is accomplished by detecting and aligning to the 8B/10B K28.5 codeword. The ...

Page 9

DUAL GIGABIT ETHERNET TRANSCEIVER Table 5. Transmitter Input Signals Assignment and Descriptions ...

Page 10

S2068 Table 7. Receiver Output Signals Assignment and Descriptions ...

Page 11

DUAL GIGABIT ETHERNET TRANSCEIVER Table 8. Receiver Input Signals Assignment and Descriptions ...

Page 12

S2068 Table 11. Power and Ground Signals Assignment and Descriptions ...

Page 13

DUAL GIGABIT ETHERNET TRANSCEIVER Figure 7. S2068 Pinout (Bottom View ...

Page 14

S2068 Figure 8. S2068 Pinout (Top View ...

Page 15

DUAL GIGABIT ETHERNET TRANSCEIVER Figure 9. 156 TBGA Package Thermal Management Device S2068 October 13, 2000 / Revision 19.8˚C/W 3.5˚C/W S2068 15 ...

Page 16

S2068 Figure 10. Transmitter Timing (REFCLK Mode, TMODE = 0) REFCLK DINx[0:9] SERIAL DATA OUT Table 12. S2068 Transmitter Timing (REFCLK Mode, TMODE = ...

Page 17

DUAL GIGABIT ETHERNET TRANSCEIVER Table 14. Transmitter Timing ...

Page 18

S2068 Figure 13. Receiver Timing (Full Clock Mode, CMODE = 1) SERIAL DATA IN RBC0x RBC1x DOUTx[0:9], COM_DETx Table 16. S2068 Receiver Timing (Full Clock Mode, CMODE = ...

Page 19

DUAL GIGABIT ETHERNET TRANSCEIVER Table 18. S2068 Receiver Timing ...

Page 20

S2068 Table 19. Absolute Maximum Ratings ...

Page 21

DUAL GIGABIT ETHERNET TRANSCEIVER Table 22. DC Characteristics ...

Page 22

S2068 OUTPUT LOAD The S2068 serial outputs require a resistive load to set the output current. The recommended resistor value is 4 ground. This value can be varied to adjust drive current, signal voltage swing, and power usage ...

Page 23

DUAL GIGABIT ETHERNET TRANSCEIVER Figure 22. Loop Filter Capacitor Connections October 13, 2000 / Revision D 270 CAP1 22 nf CAP2 270 S2068 S2068 23 ...

Page 24

... Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 • (800) 755-2622 • Fax: (858) 450-9885 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current ...

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