SLXT973QE Cortina Systems Inc, SLXT973QE Datasheet - Page 19

• Manufacturer Part Number: SLXT973QE
• Manufacturer: Cortina Systems Inc

Specifications of SLXT973QE

• Lead Free Status / RoHS Status: Not Compliant

LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
Table 3
Table 4
Cortina Systems
Port 1 Signal Descriptions (Sheet 2 of 2)
Network Interface Signal Descriptions (Sheet 1 of 2)
®
3
4
19
22
23
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
1. AI = Analog Input, AO = Analog Output, I = Input, O = Output, OD = Open Drain output,
Pin #
Pin #
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
59
60
63
64
76
ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output,
IP = Weak Internal Pull-up, ID = Weak Internal Pull-Down
DPAN_0
DPBP_0
DPBN_0
DPAP_0
Names
Signal
COL1
CRS1
MDDIS1
MDC1
MDIO1
Signal Names
SD0
RX+
TX+
RX-
TX-
TP
Op
–
Type
O,
O,
Fiber
RX+
TX+
RX-
TX-
Op
I/O
–
I
I
S
S
1
Port
Collision Detected. The LXT973 Transceiver asserts this output
when a collision is detected. This output remains High for the duration
of the collision. COL is asynchronous and is inactive during full-duplex
operation.
Carrier Sense. During half-duplex operation, the LXT973 Transceiver
asserts this output when either the transmit or receive medium is non-
idle. During full-duplex operation, CRS1 is asserted only when receive
medium is non-idle.
Management Disable. When MDDIS is tied High, the MDIO port is
completely disabled and the Hardware Control Interface pins set their
respective bits at power-up and reset.
When MDDIS is pulled Low at power-up or reset via the internal pull-
down resistor or by tieing it to ground, the Hardware Control Interface
Pins control only the initial or “default” values of their respective
register bits. After the power-up/reset cycle is complete, bit control
reverts to the MDIO serial channel.
Management Data Clock. Clock for MDIO1 serial channel. Maximum
frequency is 20 MHz.
(Note:
of product.)
Management Data Input/Output. Bidirectional serial data channel for
PHY/STA communication.
0
0
0
0
–
T
T
Type
Pair
20 MHz value to be verified prior to final production release
A
A
B
B
–
AI/AO,
AI/AO,
Type
SL
SL
I
1
Twisted-Pair/Fiber Pair A, Positive &
Negative - Port 0. Differential pair produces
or receives IEEE 802.3-compliant pulses for
either 100BASE-TX or 10BASE-T.
Also acts as receiver in Fiber mode.
Twisted-Pair/Fiber Pair B, Positive &
Negative - Port 0. Differential pair produces
or receives IEEE 802.3-compliant pulses for
either 100BASE-TX or 10BASE-T.
Also acts as transmitter in Fiber mode.
Signal Detect. This signal is used for signal
quality indication in Fiber mode. In twisted-
pair mode, this pin should be tied to GND.
Signal Description
Signal Description
2.0 Signal Descriptions
Page 19