SLXT973QE Cortina Systems Inc, SLXT973QE Datasheet - Page 30

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SLXT973QE

Manufacturer Part Number
SLXT973QE
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of SLXT973QE

Lead Free Status / RoHS Status
Not Compliant
LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
3.4.2
3.4.2.1
3.4.2.2
3.5
3.5.1
3.5.2
Cortina Systems
Clock Requirements
Reference Clock / External Oscillator
The LXT973 Transceiver requires a constant enabled reference clock (REFCLK).
REFCLK frequency must be 25 MHz. Considering overall system performance first, the
clock is best derived by providing a crystal-based oscillator. PLL-based oscillators with
known stability may also be used. In general, an oscillator-based clock source is
recommended over a derived clock due to frequency stability and overall signal integrity.
Regardless of clock source, careful consideration should be given to physical placement,
board layout, and signal routing of the source to maintain the highest possible level of
signal integrity. Refer to
MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data
clock (MDC) speed is a maximum of 20 MHz. Refer to
Initialization
When the LXT973 Transceiver is first powered on, reset, or encounters a link failure state,
it checks the MDIO register configuration bits to determine the line speed and operating
conditions to use for the network link. The configuration bits may be set by the Hardware
Control or MDIO interface as shown in
MDIO Control Mode
In the MDIO Control mode, the LXT973 Transceiver reads the Hardware Control Interface
pins to set the initial (default) values of the MDIO registers. Once the initial values are set,
bit control reverts to the MDIO interface.
Hardware Control Mode
In the Hardware Control Mode, the LXT973 Transceiver disables direct write operations to
the MDIO registers via the MDIO Interface. On power-up or hardware reset the LXT973
Transceiver reads the Hardware Control Interface pins and sets the MDIO registers
accordingly.
The following modes are available using either Hardware Control or MDIO Control:
When the network link is forced to a specific configuration, the LXT973 Transceiver
immediately begins operating the network interface as commanded. When auto-
negotiation is enabled, the LXT973 Transceiver begins the auto-negotiation/parallel-
detection operation.
®
• Forced network link to 100BASE-FX (Fiber)
• Forced network link operation to:
• Allow auto-negotiation/parallel-detection
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
100BASE-TX, full-duplex
100BASE-TX, half-duplex
10BASE-T, full-duplex
10BASE-T, half-duplex
Table 33 on page 78
Table 9 on page
for clock timing requirements.
Table 49 on page 89
32.
3.5 Initialization
for details.
Page 30

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