SLXT973QE Cortina Systems Inc, SLXT973QE Datasheet - Page 39

• Manufacturer Part Number: SLXT973QE
• Manufacturer: Cortina Systems Inc

Specifications of SLXT973QE

• Lead Free Status / RoHS Status: Not Compliant

LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
3.8.4.4
3.8.4.5
3.8.5
3.8.5.1
Cortina Systems
Scrambler/Descrambler
The purpose of the scrambler is to spread the signal power spectrum and further reduce
EMI using an 11-bit, non-data-dependent polynomial. The receiver automatically decodes
the polynomial whenever IDLE symbols are received.
The scrambler/de scrambler can be bypassed by setting Register bit 16.12 = 1. The
scrambler is automatically bypassed when the fiber port is enabled. Scrambler bypass is
provided for diagnostic and test support.
Baseline Wander Correction
The LXT973 Transceiver provides a baseline wander correction function which makes the
device robust under all network operating conditions. The MLT3 coding scheme used in
100BASE-TX is, by definition, “unbalanced.” This means that the DC average value of the
signal voltage can “wander” significantly over short time intervals (tenths of seconds). This
wander may cause receiver errors, particularly in less robust designs, at long-line lengths
(100 meters). The exact characteristics of the wander are completely data dependent.
The LXT973 Transceiver baseline wander correction characteristics allow the device to
recover error-free data while receiving worst-case “killer” packets over all cable lengths.
Fiber PMD Sublayer
The LXT973 Transceiver provides an LVPECL interface for connection to an external
3.3 V or 5 V fiber-optic transceiver. (The external transceiver provides the PMD function
for the optical medium.) The LXT973 Transceiver uses a 125 Mbaud NRZI format for the
fiber interface, and does not support 10BASE-FL applications.
Far End Fault Indications
The LXT973 Transceiver Signal Detect pins independently detect signal faults from the
local fiber transceivers via the SD pins. The device also uses Register bit 1.4 to report
Remote Fault indications received from its link partner. The device ORs both fault
conditions to set Register bit 1.4. This bit is set once and cleared when read.
Either fault condition causes the LXT973 Transceiver to drop the link unless Forced Link
Pass is selected (Register bit 16.14 = 1). A link-down condition is then reported via status
bits.
In response to locally detected signal faults (SD activated by the local fiber transceiver),
the affected port can transmit the Far End Fault code if a fault code transmission is
enabled by Register bit 16.2.
The occurrence of a Far End Fault causes all transmission of data from the Reconciliation
Sublayer to stop and the Far End fault code to begin. The Far End Fault code consists of
84 “1s” followed by a single “0”, and is repeated until the Far End Fault condition is
removed.
®
• When Register bit 16.2 = 1, transmission of the Far End Fault code is enabled. The
• When Register bit 16.2 = 0, the LXT973 Transceiver does not transmit Far End Fault
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
LXT973 Transceiver transmits Far End Fault code if fault conditions are detected by
the Signal Detect pins.
code. It continues to transmit IDLE code and may or may not drop link, depending on
the setting for Register bit 16.14.
3.8 100 Mbps Operation
Page 39