SLXT973QE Cortina Systems Inc, SLXT973QE Datasheet - Page 57

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SLXT973QE

Manufacturer Part Number
SLXT973QE
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of SLXT973QE

Lead Free Status / RoHS Status
Not Compliant
LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
8.0
8.1
Figure 19
Figure 20
Cortina Systems
100 Mbps Operation
The MAC passes data to the LXT973 Transceiver over the MII. The LXT973 Transceiver
encodes and scrambles the data, then transmits it using MLT-3 (for 100BASE-TX-over-
copper), or NRZI signaling (for 100BASE-FX-over-fiber). The LXT973 Transceiver
descrambles and decodes MLT-3 data received from the network. When the MAC is not
actively transmitting data, the
LXT973 Transceiver sends out IDLE symbols on the line.
As shown in
pattern. When TXEN is asserted, the LXT973 Transceiver transmits a /J/K/ symbol to the
network (Start of Stream Delimiter or SSD). It then encodes and transmits the rest of the
packet, including the balance of the preamble, the SFD (Start of Frame Delimiter), packet
data, and CRC. Once the packet ends, the LXT973 Transceiver transmits the /T/R/symbol
(End-of-Stream Delimiter (ESD)) and then returns to transmitting IDLE symbols.
The encoder translates the 4-bit nibbles into 5-bit symbols, which are sent over the
100BASE-TX connection. A fifth bit is provided on pins TXER0 and TXER1 during symbol
mode to allow a 5-bit symbol to be sent across the MII interface. The 5B encoder is
bypassed in symbol mode.
Figure 20 on page 57
Displaying Symbol Errors
The PHY provides the MAC with an indication of errors that occur during the receive
process. This output is called RXER. It is possible to map the symbol error detection
output to the RXER pin using Register bit 26.9. In normal mode (Register bit 26.9 = 0), the
RXER output is active per the IEEE 802.3 standard. When this register bit = 1, the RXER
output goes active only when a symbol error is detected. This provides a quick measure of
bit error rate.
100BASE-TX Frame Format
100BASE-TX Data Path
®
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Replaced by
/J/K/ code-groups
Start-of-Stream
Delimiter (SSD)
Standard MII Mode Data Flow
P0
D0
D1
D2
D3
64-Bit Preamble
P1
(8 Octets)
Parallel
Parallel
Serial
Serial
Figure 19 on page
P6
to
to
Delimiter (SFD)
Start-of-Frame
SFD
D0 D1 D2 D3
shows the data conversion flow from nibbles to symbols.
DA
Address (6 Octets each)
Destination and Source
DA
SA
57, the MAC starts each transmission with a preamble
4B/5B
5B/4B
SA
Packet Length
L1
S0 S1 S2 S3 S4
(2 Octets)
L2
(Pad to minimum packet size)
D0
Data Field
D1
Scramble
Scramble
Dn
De-
Frame Check Field
(4 Octets)
CRC
8.0 100 Mbps Operation
MLT3
End-of-Stream Delimiter (ESD)
/T/R/ code-groups
pattern: 0, +1, 0, -1, 0, +1...
All transitions must follow
Replaced by
0
InterFrame Gap / Idle Code
No Transition = 0.
I0
Transition = 1.
+1
(> 12 Octets)
0
IFG
-1
Page 57
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