SLXT973QE Cortina Systems Inc, SLXT973QE Datasheet - Page 88

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SLXT973QE

Manufacturer Part Number
SLXT973QE
Description
Manufacturer
Cortina Systems Inc
Datasheet

Specifications of SLXT973QE

Lead Free Status / RoHS Status
Not Compliant
LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
Figure 37
Figure 38
Table 48
Cortina Systems
Fast Link Pulse Timing
FLP Burst Timing
Fast Link Pulse Timing Parameters
®
Clock/Data pulse width
Clock pulse to Data pulse
Clock pulse to Clock pulse
FLP burst width
FLP burst to FLP burst
Clock/Data pulses per burst
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
Note:
Twisted-Pair
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Note:
Twisted-Pair
production testing.
Output
Twisted-pair output default pins are as follows: DPAP/N_0 and DPBP/N_1.
Output
Twisted-pair output default pins are as follows: DPAP/N_0 and DPBP/N_1.
Parameter
FLP Burst
Clock Pulse
t4
t1
Sym
t1
t2
t3
t4
t5
t2
55.5
Min
115
111
17
8
t5
Data Pulse
Typ
116
126
2.0
63
10
t1
t3
1
Max
69.5
118
139
24
33
FLP Burst
Units
ms
ms
Clock Pulse
ns
μ s
μ s
ea
15.0 Timing Diagrams
Conditions
Test
Page 88

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