WBLXT9785EHC.D0 Intel, WBLXT9785EHC.D0 Datasheet - Page 129
WBLXT9785EHC.D0
Manufacturer Part Number
WBLXT9785EHC.D0
Description
Manufacturer
Intel
Datasheet
1.WBLXT9785EHC.D0.pdf
(221 pages)
Specifications of WBLXT9785EHC.D0
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LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 43
Cortina Systems
The Serial MII operates at 125 MHz using a global reference clock and frame
synchronization signal (REFCLK and SYNC). Each port has an individual two-line data
interface (TxDatan and RxDatan). All signals are synchronous to REFCLK.
summarizes the SMII signals.
Data is exchanged in 10-bit serial words. Each word contains one data byte (two nibbles
of 4B coded data) and two status bits. When the port is operating at 100 Mbps, each word
contains a new data byte. When the port is operating at 10 Mbps, each data byte is
repeated 10 times.
SMII Signal Summary
®
TxData
SYNC
RxData
REFCLK
1. Refer to
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal
on page 39
Table 7, SMII Specific Signal Descriptions – PQFP,
PHY
PHY
MAC
MAC &
PHY
for detailed signal descriptions.
To
MAC
MAC
PHY
System
From
Transmit data & control
Synchronization
Receive data & control
Synchronization
Purpose
4.7 Serial MII Operation
Table 43
Page 129
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