WBLXT9785EHC.D0 Intel, WBLXT9785EHC.D0 Datasheet - Page 142
WBLXT9785EHC.D0
Manufacturer Part Number
WBLXT9785EHC.D0
Description
Manufacturer
Intel
Datasheet
1.WBLXT9785EHC.D0.pdf
(221 pages)
Specifications of WBLXT9785EHC.D0
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LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
4.9.2.1.1
Figure 28
4.9.3
Table 46
Cortina Systems
Preamble Handling
When the MAC asserts TxEN, the PCS substitutes a /J/K/ symbol pair, also known as the
Start-of-Stream Delimiter (SSD), for the first two nibbles received across the RMII. The
PCS layer continues to encode the remaining RMII data until TxEN is de-asserted (see
Table 46 on page
The PCS layer performs the opposite function in the receive direction by substituting two
preamble nibbles for the SSD.
Protocol Sublayers
PMA Sublayer
The 100BASE-X PMA protocol uses the 4B/5B data encoding scheme to encode/decode
the data streams. The coding scheme is shown in
4B/5B Coding
®
1. The /I/ (Idle) code group is sent continuously between frames.
2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.
3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.
4. An /H/ (Error) code group is used to signal an error condition.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Code Type
Sublayer
Sublayer
Sublayer
PMD
PMA
PCS
142). It then returns to supplying IDLE symbols to the line driver.
4B Code
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
LXT9785
De-scrambler
Scrambler/
Name
100BASE-TX
Serializer/De-serializer
0
1
2
3
4
5
Link/Carrier Detect
Encoder/Decoder
4 3 2 1 0
5B Code
1 1 1 1 0
0 1 0 0 1
1 0 1 0 0
1 0 1 0 1
0 1 0 1 0
0 1 0 1 1
MII Interface
Table
Fiber Transceiver
46.
100BASE-FX
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
LVPECL Interface
4.9 100 Mbps Operation
Interpretation
Page 142
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