WBLXT9785EHC.D0 Intel, WBLXT9785EHC.D0 Datasheet - Page 181
WBLXT9785EHC.D0
Manufacturer Part Number
WBLXT9785EHC.D0
Description
Manufacturer
Intel
Datasheet
1.WBLXT9785EHC.D0.pdf
(221 pages)
Specifications of WBLXT9785EHC.D0
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LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 69
Figure 48
Table 70
Cortina Systems
SS-SMII - 100BASE-FX Receive Timing Parameters
SS-SMII - 100BASE-FX Transmit Timing
SS-SMII - 100BASE-FX Transmit Timing Parameters
®
REFCLK rising edge to RxCLK rising edge
RxData/RxSYNC output delay from RxCLK
rising edge
RxData/RxSYNC Rise/Fall time
Receive start of /J/ to CRS asserted
Receive start of /T/ to CRS de-asserted
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Note:
TxSYNC setup to TxCLK rising edge and
TxData setup to TxCLK rising edge
TxSYNC hold from TxCLK rising edge and
TxData hold to TxCLK rising edge
TxData to TPFO Latency
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. “BT” signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using
Note:
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
testing.
100BASE-TX or 100BASE-FX).
testing.
100BASE-TX or 100BASE-FX).
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a
default configuration of 00 (32 bits of initial fill).
TxSYNC
TxData
TxCLK
TPFO
Parameter
Parameter
t
1
t
2
Sym
t
3
t1
t2
t3
t4
t5
Sym
t1
t2
t3
Min
1.5
–
–
–
–
Min
1.5
1.0
–
Typ1
1.5
18
21
–
1
Typ1
11
t
–
–
1
Max
23
26
t
5
–
2
Max
13
–
–
Units
BT
BT
ns
ns
ns
Units
2
2
BT
ns
ns
6.0 Test Specifications
2
Minimum C
Maximum C
Test Conditions
Test Conditions
–
–
–
–
L
L
–
–
–
Page 181
= 5pF
= 40pF
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