WBLXT9785EHC.D0 Intel, WBLXT9785EHC.D0 Datasheet - Page 206
WBLXT9785EHC.D0
Manufacturer Part Number
WBLXT9785EHC.D0
Description
Manufacturer
Intel
Datasheet
1.WBLXT9785EHC.D0.pdf
(221 pages)
Specifications of WBLXT9785EHC.D0
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Compliant
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LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
Table 99
Cortina Systems
RMII Out-of-Band Signaling Register (Address 25, Hex 19)
®
1. R/W = Read/Write
Note:
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
15:0
15:7
6:4
3:1
Bit
0
The BGA15 package does not support RMII operation.
Name
Reserved for
BGA15
Reserved
BIT1
BIT0
PROGRMII
Description
Write as 0, ignore on Read.
Write as 0, ignore on Read
These three bits select which status information is
available on the RxData(1) bit of the RMII bus.
000 =Link
001 =Speed
010 =Duplex
011 = Auto-negotiation complete
100 =Polarity reversed
101 =Jabber detected
110 = Interrupt pending
111 = Reserved
These three bits select which status information is
available on the RxData(0) bit of the RMII bus.
000 =Link
001 =Speed
010 =Duplex
011 = Auto-negotiation complete
100 =Polarity reversed
101 =Jabber detected
110 = Interrupt pending
111 = Reserved
0 = Disable Out-of-Band signaling.
1 = Enable programmable RMII Out-of-Band
Note: Out-of-Band signaling is disabled when the
Isolate mode is enabled by setting Register bit 0.10.
signaling. When enabled, Register bits 6:1 specify
which status bits are available on the RMII
RxData data bus.
PQFP and BGA23
BGA15
7.0 Register Definitions
Type
R/W
R/W
R/W
R/W
R/W
1
Page 206
Default
0x0000
0x000
000
000
0
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